DocID026333 Rev 4

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HTS221

Digital interfaces

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the current-source pull-up circuit for the SCLH signal. As other devices can delay the serial

enable its current-source pull-up circuit when all devices have released the SCLH line and

the SCLH signal has reached a HIGH level, thus speeding up the last part of the rise time of

the SCLH signal. The active master then sends a repeated START condition (Sr) followed

by a 7-bit slave address (or 10-bit slave address; see previous section) with a R/W bit

address, and receives an acknowledge bit (A) from the selected slave.

After a repeated START condition and after each acknowledge bit (A) or not-acknowledge

bit (A), the active master disables its current-source pull-up circuit. This enables other

devices to delay the serial transfer by stretching the LOW period of the SCLH signal. The

active master re-enables its current-source pull-up circuit again when all devices have

released and the SCLH signal reaches a HIGH level, and so speeds up the last part of the

SCLH signal’s rise time. Data transfer continues in HS-mode after the next repeated START

(Sr), and only switches back to F/S-mode after a STOP condition (P). To reduce the

overhead of the master code, it’s possible that a master links a number of HS-mode

transfers, separated by repeated START conditions (Sr).

5.2

SPI bus interface (CS = LOW)

The HTS221 SPI is a slave bus that can operate in 0 and 3 SPI modes. The SPI allows

writing to and reading from the registers of the device. The serial interface interacts with the

application through 3 wires: CS, SPC, SDI/SDO.

CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the

transmission and goes back high at the end. SCL is the serial port clock and it is controlled

by the SPI master. It is stopped high when CS is high (no transmission). SDI/SDO is the

serial port data input and output. This line is driven at the falling edge of SCL and should be

captured at the rising edge of SCL.

Both the read register and write register commands are completed in 16 clock pulses or in

multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling

edges of SCL. The first bit (bit 0) starts at the first falling edge of SCL after the falling edge

of CS while the last bit (bit 15, bit 23,...) starts at the last falling edge of SCL just before the

rising edge of CS.