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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM8AL3188TCX датащи(PDF) 83 Page - STMicroelectronics |
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STM8AL3188TCX датащи(HTML) 83 Page - STMicroelectronics |
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83 / 131 page  DocID027179 Rev 6 83/131 STM8AL318x STM8AL3L8x Electrical parameters 117 9.3.4 Clock and timing characteristics HSE external clock (HSEBYP = 1 in CLK_ECKCR) Subject to general operating conditions for VDD and TA. 5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD /2. Floating DAC output. 6. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2 enabled with static inputs. Supply current of internal reference voltage excluded. 7. Including supply current of internal reference voltage. Table 29. Current consumption under external reset Symbol Parameter Conditions Typ. Unit IDD(RST) Supply current under external reset (1) PB1/PB3/PA5 pins are externally tied to VDD VDD = 1.8 V 48 µA VDD = 3 V 80 VDD = 3.6 V 95 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger. Table 30. HSE external clock characteristics Symbol Parameter Conditions Min. Typ. Max. Unit fHSE_ext(1) External clock source frequency - 1- 16 MHz VHSEH OSC_IN input pin high- level voltage 0.7 x VDD -VDD V VHSEL OSC_IN input pin low- level voltage VSS - 0.3 x VDD Cin(HSE)(1) OSC_IN input capacitance - - 2.6 - pF ILEAK_HSE OSC_IN input leakage current VSS < VIN < VDD -- ±500 nA 1. Guaranteed by design. |
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