PM7345 datasheet(51/306 Pages) PMC

51 / 306 page

PM7345 S/UNI-PDH

DATA SHEET

PMC-931011

ISSUE 6

SATURN USER-NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

C13/CADD

8KREF

Input

Transmit Stuff Control (C13/CADD). C13/CADD

controls stuffing when configured for DS3 or G.751

E3 PLCP frame formats and when the 8KREF bit in

the S/UNI-PDH Control Register is set to logic 0.

When DS3 PLCP format is enabled, C13/CADD

determines whether to use a 13 or 14 nibble trailer

at the next stuff opportunity. When logic 0, a 14

nibble trailer is used. When logic 1, a 13 nibble

trailer is used.

When G.751 E3 PLCP format is enabled,

C13/CADD determines whether to add or subtract

one octet from the internally generated octet stuff

pattern at the next stuff opportunity. When logic 0,

one octet is subtracted from the next 18, 19, or 20

octet trailer. When logic 1, one octet is added to the

next 18, 19, or 20 octet trailer.

C13/CADD is internally synchronized and thus can

be asynchronous.

8 kHz Reference Input (8KREF). The PLCP frame

rate can be locked to an external 8 kHz reference

applied on this input when the 8KREF bit in the

S/UNI-PDH Control Register is set to logic 1. An

internal phase-frequency detector compares the

transmit PLCP frame rate with the externally applied

8 kHz reference and adjusts the PLCP frame rate

by taking control over the internal C13/CADD signal.

The 8KREF input must transition high once every

125

µs for correct operation. The 8KREF input is

treated as an asynchronous signal and must be

“glitch-free”. The minimum high or low period of the

8KREF pin is 20 ns. Only the rising edge is used.

SYFIFOB

Input

n/a

Synchronous FIFO Enable (SYFIFOB). This

active low signal selects between the synchronous

and asynchronous FIFO interfaces on the system

side. This signal is available only in the 100-pin

PQFP package and must be tied to VSS to enable

the synchronous FIFO interface. SYFIFOB is not

available in the 84-pin PLCC package and is pulled

to logic 1 internally by an integral pull-up resistor,

thus selecting the asynchronous FIFO interface.

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