PM7345 datasheet(41/306 Pages) PMC

41 / 306 page

PM7345 S/UNI-PDH

DATA SHEET

PMC-931011

ISSUE 6

SATURN USER-NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

FWRB/

TFCLK

Input

FIFO Write (FWRB). FWRB writes cell octets to the

transmit FIFO. The data present on the

FWDATA[7:0] bus is written into the transmit FIFO

on the rising edge of FWRB. TSOC is sampled on

the falling edge of FWRB.

Transmit FIFO Write Clock (TFCLK). TFCLK is

used to write bytes into the synchronous transmit

FIFO interface. This interface is only available in the

100-pin PQFP package when the synchronous

FIFO interface is enabled (SYFIFOB tied to logic 0).

TFCLK must cycle at a 25 MHz or lower

instantaneous rate. TWRENB, TSOC, TXPRTY, and

FWDATA[7:0] are all sampled on the rising edge of

TFCLK. TCA is updated on the rising edge of

TFCLK.

TWRENB

Input

n/a

Transmit FIFO Write Enable (TWRENB). This

active low enable signal is used to initiate writes into

the transmit FIFO. TWRENB is sampled on the

rising edge of TFCLK. When TWRENB is sampled

as a logic 0, the byte sampled on the FWDATA[7:0]

bus is written to the transmit FIFO. When TWRENB

is sampled as a logic 1, no write is performed. A

complete 53 byte cell must be written to the FIFO

before it is inserted into the transmission layer.

Idle/Unassigned cells are inserted when a complete

cell is not available. The TWRENB signal is only

available in the 100-pin PQFP package when

SYFIFOB is tied to logic 0. TWRENB contains an

integral pull-down resistor.

TCELL

Output

Transmit Cell Indication (TCELL). TCELL pulses

once for every cell transmitted. TCELL is updated

using timing derived from the transmit input clock

(TICLK) and is active for a minimum of 8 TICLK

periods. TCELL is forced to logic 0 when in the

FIFO bypass mode.

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