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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM642 датащи(PDF) 33 Page - Texas Instruments |
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TMS320DM642 датащи(HTML) 33 Page - Texas Instruments |
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33 / 178 page  www.ti.com TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 Table 2-4. Terminal Functions (continued) SIGNAL IPD/ TYPE(1) DESCRIPTION IPU(2) NAME NO. GP0[15]/PRST(3) G3 General-purpose input/output (GP0) 15 pin (I/O/Z) or PCI reset (I). GP0 14 pin (I/O/Z) or PCI clock (I) GP0[14]/PCLK(3) C1 GP0 13 pin (I/O/Z) or PCI interrupt A (O/Z) GP0[13]/PINTA(3) G4 GP0 12 pin (I/O/Z) or PCI bus grant (I) GP0 11 pin (I/O/Z) or PCI bus request (O/Z) GP0[12]/PGNT(3) H4 I/O/Z GP0 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z) GP0[11]/PREQ(3) F1 GP0 9 pin (I/O/Z) or PCI initialization device select (I) GP0[10]/PCBE3(3) J2 Note: By default, no function is enabled upon reset. To configure these pins, see the Device Configuration section of this data sheet. GP0[9]/PIDSEL(3) K3 GP0 3 pin (I/O/Z) Boot Configuration: PCI EEPROM Auto-Initialization (EEAI). GP0[3] L5 I/O/Z IPD 0 - PCI auto-initialization through EEPROM is disabled (default). 1 - PCI auto-initialization through EEPROM is enabled VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC) output [output only] [default] or this pin can be programmed as a GP0 8 pin (I/O/Z) Boot Configuration: PCI frequency selection (PCI66). If the PCI peripheral is enabled (PCI_EN pin = 1), then: 0 - PCI operates at 66 MHz (default). VDAC/GP0[8]/PCI66(3) AD1 I/O/Z IPD 1 - PCI operates at 33 MHz. The –500 device supports PCI at 33 MHz only. For proper –500 device operation when the PCI peripheral is enabled (PCI_EN = 1), this pin must be pulled up with a 1-k Ω resistor at device reset. Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. EMIFA (64-bit) – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ACE3 L26 O/Z IPU EMIFA memory space enables ACE2 K23 O/Z IPU • Enabled by bits 28 through 31 of the word address ACE1 K24 O/Z IPU • Only one pin is asserted during any external data access ACE0 K25 O/Z IPU ABE7 T22 O/Z IPU ABE6 T23 O/Z IPU EMIFA byte-enable control ABE5 R25 O/Z IPU • Decoded from the low-order address bits. The number of address bits or ABE4 R26 O/Z IPU byte enables used depends on the width of external memory. ABE3 M25 O/Z IPU • Byte-write enables for most types of memory ABE2 M26 O/Z IPU • Can be directly connected to SDRAM read and write mask signal (SDQM) ABE1 L23 O/Z IPU ABE0 L24 O/Z IPU EMIFA peripheral data transfer, allows direct transfer between external APDT M22 O/Z IPU peripherals EMIFA (64-bit) – BUS ARBITRATION AHOLDA N22 O IPU EMIFA hold-request-acknowledge to the host AHOLD W24 I IPU EMIFA hold request from the host ABUSREQ P22 O IPU EMIFA bus request output Device Overview 33 |
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