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TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

5.1.1.2

Signal Transition Rates

All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).

5.1.1.3

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis application report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external

device and from the external device to the DSP. This round-trip delay tends to negatively impact the input

setup time margin, but also tends to improve the input hold time margins (see Table 5-1 and Figure 5-4).

Figure 5-4 represents a general transfer between the DSP and an external device. The figure also

represents board route delays and how they are perceived by the DSP and the external device.

Table 5-1. Board-Level Timing Example

(see Figure 5-4)

NO.

DESCRIPTION

Clock route delay

Minimum DSP hold time

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

DM642 Peripheral Information and Electrical Specifications

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