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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM642 датащи(PDF) 39 Page - Texas Instruments |
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TMS320DM642 датащи(HTML) 39 Page - Texas Instruments |
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39 / 178 page  www.ti.com TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 Table 2-4. Terminal Functions (continued) SIGNAL IPD/ TYPE(1) DESCRIPTION IPU(2) NAME NO. VIDEO PORT 0 (VP0) OR McASP0 CONTROL OR McBSP0 VP0D[19]/AHCLKX0(3) AC12 VP0D[18]/AFSX0(3) AD12 VP0D[17]/ACLKX0(3) AB13 VP0D[16]/AMUTE0(3) AC13 VP0D[15]/ AD13 AMUTEIN0(3) VP0D[14]/AHCLKR0(3) AB14 Video port 0 (VP0) data input/output (I/O/Z) or McASP0 control pins (I/O/Z) VP0D[13]/AFSR0(3) AC14 [default] and Video port 0 (VP0) data input/output (I/O/Z) or McBSP0 data VP0D[12]/ACLKR0(3) AD14 input/output (I/O/Z) [default] VP0D[11] AB15 By default, standalone VP0 data input/output pins have no function enabled VP0D[10] AC15 I/O/Z IPD upon reset. To configure these pins, see the Device Configuration section of this data sheet. VP0D[9] AD15 For more details on the McBSP0 pin functions or the McASP0 control pin VP0D[8]/CLKR0(3) AE15 functions, see McBSP0 or McASP0 control sections of this table and the Device VP0D[7]/FSR0(3) AB16 Configurations section of this data sheet. VP0D[6]/DR0(3) AC16 VP0D[5]/CLKS0(3) AD16 VP0D[4]/DX0(3) AE16 VP0D[3]/FSX0(3) AF16 VP0D[2]/CLKX0(3) AF17 VP0D[1] AE18 VP0D[0] AF18 VP0CLK1 AF12 I/O/Z IPD VP0 clock 1 (I/O/Z) VP0CLK0 AF14 I IPD VP0 clock 0 (I) VP0CTL2 AD17 VP0 control 2 (I/O/Z) VP0CTL1 AC17 I/O/Z IPD VP0 control 1 (I/O/Z) VP0CTL0 AE17 VP0control 0 (I/O/Z) TIMER 2 – No external pins. The timer 2 peripheral pins are not pinned out as external pins. TIMER 1 Timer 1 output (O/Z) Boot Configuration: Device endian mode [LENDIAN] (I) Controls initialization of DSP modes at reset via pullup/pulldown resistors • Device Endian mode TOUT1 B5 O/Z IPU 0 - Big Endian 1 - Little Endian (default) For more details on LENDIAN, see the Device Configurations section of this data sheet. TINP1 A5 I IPD Timer 1 or general-purpose input TIMER 0 Timer 0 output (O/Z) Boot Configuration: MAC enable pin [MAC_EN] (I) The PCI_EN and the MAC_EN pin control the selection (enable/disable) of the TOUT0 C5 O/Z IPD HPI, EMAC, MDIO, and GP0[15:9], or PCI peripherals. The pins work in conjunction to enable/disable these peripherals. For more details, see the Device Configurations section of this data sheet. TINP0 A4 I IPD Timer 0 or general-purpose input Device Overview 39 |
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