CS8401 datasheet(15/34 Pages) ETC

15 / 34 page

Buffer-Read and Interrupt Timing

As mentioned previously in the buffer mode sec-

tions, conflicts between externally writing to the

buffer ram and the CS8401A internally reading

bytes of ram for transmission may be averted by

using the flag levels to avoid the section cur-

rently being addressed by the part. Interrupts

occur at flag edges indicating the exact byte that

the part is currently reading. Utilizing INT along

with the flags, the byte currently being read by the

part can be avoided allowing access to all other

bytes instead of just a section. Figure 15 illustrates

the timing between flags, INT, and the internal

reading of the buffer for transmission. The mas-

ter clock IMCK is shown as 128

×Fs. Other

MCK frequencies are initially divided to obtain

128

×Fs, defined as IMCK (internal MCK),

which is then used for all internal timing, so the

timing in Figure 15 is valid for all MCK fre-

quencies. When the parity bit (P) is transmitted, a

transition on a flag causes INT to go low if the

appropriate mask bit is set. Concurrently, the part

starts reading from the internal buffer. Writing to

the buffer ram location being read by the part

should be avoided while the internal "ram read"

signal is high.

Flag 0

Flag 1

Flag 2

Block

(384 Audio Samples)

Left C.S. Ad.

123

4567

C.S. Byte

(Addresses are in Hex)

(Expanded)

Flag 0

Left C.S. Ad.

User Address

0B 0C

0F 08

0F 0C

13 14

14 10

17 14

Right C.S. Ad.

Flag 1

Figure 14. CS8401A Buffer Memory Read Sequence - MODE 2

IMCK

Flags 0 & 1

(128Fs)

RAM Read

Transmit Preamble

INT

TXP

TXN

Flag 2

Figure 15. RAM/Buffer-Read and Interrupt Timing

CS8401A

DS60F1

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