CS8401 datasheet(29/34 Pages) ETC

29 / 34 page

(619) 268-2400

Part Number: PE65612

Schott Corporation

1000 Parkers Lane Rd.

Wayzata, MN 55391

(612) 475-1173

FAX (612) 475-1786

Part Number:

67125450 - compatible with Pulse

67128990 - lower cost

67129000 - surface mount

67129600 - single shield

Scientific Conversions Inc.

42 Truman Drive

Novato, CA. 94947

(415) 8922323

Part Number:

SC916-01 - single shield

SC916-02 - surface mount

Appendix B: MCK and FSYNC Relationship

FSYNC should be derived either directly or indi-

rectly from MCK. The indirect case could be a

DSP, providing FSYNC through its serial port,

using the same master oscillator that generates

MCK. In either case, FSYNC’s relationship to

MCK is fixed and does not move. Since this ap-

pendix provides information on what would

happen if FSYNC did move with respect to

MCK, it does not apply to the majority of users.

All internal timing is derived from MCK. On the

CS8402A, MCK is always 128

×Fs. On the

CS8401A, the external MCK is programmable

and is initially divided to 128

×Fs before being

used by the part. The internal clock IMCK used

in the following discussion is always 128

×Fs re-

gardless of the external MCK pin.

After RST, the CS8401A and CS8402A syn-

chronize the internal timing to the audio data

port, more specifically FSYNC, to guarantee that

channel A is left channel data and channel B is

right channel data as per the AES/EBU specifica-

tion. If FSYNC moves with respect to IMCK,

the transmitter could lose synchronization, which

causes an internal reset.

Figure B1 shows the structure of the serial port

input, to the transmitter output. The audio data is

serially shifted into R1. PLD is an internal signal

that parallel loads R1 into the R2 buffer, and, at

the same time, the C, U, and V bits are latched.

On the CS8401A, the C, U, and V bits are held

in RAM, whereas on the CS8402A, they are

latched from external pins. The PLD signal rises

on the first SCK edge that can latch data. This is

coincident with the latching of the MSB of audio

data in MSB-first, left-justified modes. PLD

stays high for one SCK period. In the CS8402A

section, the arrows on SCK in Figure 16 indicate

w h e n PL D g o e s high. Also, SB C in th e

CS8402A CD submode is an external version of

PLD gated by the SBF input.

P C U V

Preamble

Dri-

ver

Mux

Biphase

Encode

TXP

TXN

R3 - Shift (out) Register

R2 - Audio Buffer

R1 - Shift (in) Register

SDATA

SCK

internally generated

CS8402A C,U,V Port

CS8401A Internal

Memory

PLD (load signal)

LDS (load signal)

IMCK

D Q

Internal Reset

Figure B1. Serial Port-to-Transmitter Block Diagram

CS8401A CS8402A

DS60F1

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