CS8401 datasheet(30/34 Pages) ETC

30 / 34 page

When the part is finished transmitting the pream-

ble of a sub-frame, the internal signal LDS rises

to parallel-load R2 into R3 for transmission. Af-

ter RST, the part synchronizes the audio port to

IMCK as shown in Figure B2. Since PLD is

based on FSYNC and LDS is based on IMCK, if

FSYNC moves with respect to IMCK until PLD

and LDS occur at the same time, the data would

not be properly loaded into R3. If LDS and PLD

overlap, an internal reset is initiated causing the

timing to return to the initial state shown in Fig-

ure B2.

Figure B2. Serial Ports-to-Transmitter Timing (slave mode)

Preamb.

Left 0

V UCP

Right 0

CUV0L

191R

CUV191R

Left 0

Preamb.

Right 191

V UCP

191L

Left 191

9.5

8.5

IMCK

PLD

CS8402A C,U, V

SDATA

FSYNC

SCK

CS8402A CBL

CS8401A Flags

TXN

TXP

LDS

Ordering Guide

Model

Temperature Range

Package

CS8401A-CP

0 to 70

°C*

24-Pin Plastic .3" DIP

CS8401A-IP

-40 to 85

°C

24-Pin Plastic .3" DIP

CS8401A-CS

0 to 70

°C*

24-Pin Plastic SOIC

CS8401A-IS

-40 to 85

°C

24-Pin Plastic SOIC

CS8402A-CP

0 to 70

°C*

24-Pin Plastic .3" DIP

CS8402A-IP

-40 to 85

°C

24-Pin Plastic .3" DIP

CS8402A-CS

0 to 70

°C*

24-Pin Plastic SOIC

CS8402A-IS

-40 to 85

°C

24-Pin Plastic SOIC

* Although the ’-CP’ and ’-CS’ suffixed parts are guaranteed to operate over 0 to 70

°C, they are

tested at 25

°C only. If testing over temperature is desired, the ’-IP’ and ’-IS’ suffixed parts are

tested over their specified temperature range.

CS8401A CS8402A

DS60F1

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