MODULATOR GAIN/COMPENSATION

The modulator gain is plotted out for various typical values of

components in Typical Performance characteristics. The

curves were based on the following information. The plant/

modulator gain ‘G’ is:

where Ro is the load resistance,s=j

ω, and

A1 = LC*(Ro + esr)

A2={L + R

A3=R

Here esr is the Equivalent Series Resistance of the output

capacitor, Ro is the load resistance, C is the output capaci-

tance, L is the inductance, and R

power stage (Rds+ DCR etc, typically about 40m

Ω). V

RAMP

is about 1.6V for the LM2647. The unity gain bandwidth of

the error amplifier is taken as 6.5MHz.

Let us assume Type 3 compensation Figure 15.

The design procedure is summarized in Table 2.

TABLE 2. Summary of Compensation Design Procedure

fp1

fz1

fz2

fp2

fp3

Type 3

(C1)

R2, C2

R1sR3, C3

R2, C1sC2

C3, R3

πRC, ’s’ stands for series combination.

TABLE 3.

C1

C2

C3

R2

R3

A is a factor to shift entire Gain up or down to acheive good crossover frequency and gain. Typically set A = 0.2 here.

TABLE 4.

fp1

fz1

fz2

fp2

fp3

(0)

fdp

fdb

fesr

fsw/2

πRC, ’s’ stands for series combination.

A short explanation on Table 2 follows. For example from the

table it can be seen that the second zero is created by the

series combination of R1 and R3 resonating with C3. So the

frequency of this zero is at 1/2

π(R1+R3)*C3. The solution for

calculating the component values follows. For example, C3

is set as

But where should the designer position the poles and zeroes

of the error amplifier, taking into account the modulator gain,

so as to achieve good closed loop characteristics? A typical

scenario is also provided in Table 4. For example it suggests

that both the first and second zeroes should be positioned at

the point where double pole (fdb) of the output LC filter is.

This double pole is known to occur at about.

Similarly, the esr zero occurs at fesr which is at

where C is the output capacitance

Thus all the components can be calculated easily

EVALUATION BOARD DETAILS

The Bill of Materials is now provided for the LM2647 Evalu-

ation board. The schematic is the Typical Application circuit.

See Layout Guidelines for more guidance on preferred lay-

out practices and also refer to Application Note AN-1229.

Note that a dual FET pack has been chosen for the Evalu-

ation Board.

The Evaluation board has two outputs V

3.3V as discussed under Setting Output Voltage section. The

rated load on each output is 2A continuous, and 3A peak. A

minimum load of 0.1mA should be maintained on each out-

put in SKIP mode, to ensure regulation.

20056348

FIGURE 15. Type 3 Compensation

www.national.com

22