LM2647 datasheet(18/25 Pages) NSC

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Application Information (Continued)

The case of a single input capacitor supplying two channels

running out of phase is now discussed in detail and it shows

how to formally calculate the input RMS current capability

required. The example represents a very general case in

terms of the output voltages simply to highlight the various

possible applications of the LM2647 other than its primary

intended application. One of the most important questions to

answer here is: what input voltage really gives the worst

possible (highest) input RMS current? This information is

required to size the capacitor correctly.

Example: Consider two channels running at 5V@3A and

3.3V@3A. What is the worst case input capacitor RMS cur-

rent if the input varies from 10V to 28V?

Step1: Call the output with the higher voltage as Vo1 and the

other as Vo2. Then find the ratio ‘y’ as shown below

y is clearly going to be equal to or less than 1 by definition

(since Vo2

≤ Vo1). This step is required for using the equa-

tion presented in the next step.

Step2: The equation for the input current has been derived

and it reveals that the worst-case occurs when the duty cycle

of the first channel is

where ‘y’ has been defined in Step 1. So

Therefore the appropriate input voltage to calculate the

worst case RMS input current is

Step3: Calculate the duty cycle of the other channel when

this happens

Step4: Calculate input capacitor RMS current by using the

known equation

2 = (Io12 • D1) + (Io22 • D2) - [Iol • D1+Io2 • D2]2

2 =(32 • 0.3) + (32 • 0.2) - [(3 • 0.3) + (3 • 0.2)]2

Solving

IN = 1.5A

Step5: But what is really the worst case??

It may have simply concluded at this point that "the rating of

the input capacitor must be greater or equal than 1.5A,

otherwise the life/reliability of the capacitor may be affected

severely etc.". And that is true but only under the single-point

load conditions used for the calculation. It will now be seen

that the worst case may still have gone unrecognized! What

if maximum load currents are not being drawn simulta-

neously as was assumed in our example? It can be shown

that the capacitor could actually see higher currents than

calculated in Step 4.

Suppose one channel was completely unloaded. So in effect

there is only a single output of 5V@3A. The equation for the

RMS current through the input capacitor is then

The function D(1-D) has a maxima at D = 0.5. This would

correspond to an input voltage of 5V/0.5 = 10V. And the input

capacitor current at this worst case input voltage would be

It is just a coincidence in this application that in both cases

(above and at the end of Step 4) we have calculated the

same RMS current rating for the capacitor. In general, Step

4 can certainly yield smaller values than those for a single

channel, and this may mislead us into an improper selection

of the input capacitor. It must be remembered that Step 4 is

not necessarily the worst case. We must always take the

higher of the two values so calculated.

Incidentally, the above method for a single channel is also

the method to be used to calculate the capacitor rating when

the LM2647 is formally used for single channel operation, or

if both channels are being used but separate input capaci-

tors are being allocated for each channel.

In all cases the input capacitors must be positioned physi-

cally close to their respective stages. But if separate input

capacitors are being used for each channel, the input traces

to the two inputs must be long and thin so as to introduce a

measure of high frquency decoupling between the now

separated stages.

The designer may ask, what is the use of interleaved switch-

ing if the result of the interleaved calculation in Step 4 may

not even be used in our particular example? Interleaved

switching certainly reduces cost because if the calculation

had been carried out for two non-interleaved channels

(switching in phase), both delivering maximum load, the

capacitor RMS current would have been much higher.

Note that the equations used in the above sections apply

only if the duty cycles of both channels are less than or equal

to 50% (and there is therefore no overlap in the current

waveforms). The equations for overlapping waveforms are

out of scope here.

MOSFETs

The selection of the MOSFETS should be done carefully to

maximize both efficiency and reliability together. There is a

different set of criteria for selecting the upper FET and lower

FET. It will also be seen that using very fast FETs without

deliberate thought, may seem to improve efficiency dramati-

cally on one prototype board but can impair efficiency on

another apparently ‘identical’ board, specially at light loads.

Therefore, the quest for improved efficiency must be

weighed against the possible penalty for doing this without

deeper understanding of the nuances of synchronous

switching buck stages in general. The criteria for selection

are briefly:

a) The upper FET is chosen basically for high switching

speed because in a typical synchronous buck regulator only

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