LM2645 datasheet(18/20 Pages) NSC

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Operation Descriptions (Continued)

Likewise, if the LDODRV pin is not used, connect the LD-

OFB pin to VLIN5 as shown in

Figure 4 to disable this

channel and the under voltage protection associated with it.

Switching Noise Reduction

Power MOSFETs are very fast switching devices. In syn-

chronous rectifier converter, rapid drain current rise rate of

the top FET coupled with parasitic inductance will generate

unwanted Ldi/dt spikes noise at the source node of the FET

(SWx node). The magnitude of the spike noise will increase

as the output current increases. This parasitic spike noise

may turn into electromagnetic interference (EMI) that may

cause trouble to the system performance, therefore, must be

suppressed.

As shown in

Figure 5, adding a resistor in series with the

CBOOTx pin will slowdown the gate drive (HDRVx) rise time

of the top FET to yield a desired drain current transition time.

Usually a 3.3 to 5.1 ohm resistor is sufficient to suppress the

noise. The top FET switching loss will increase with higher

resistance values.

Input Power Supply Cycling

If the input supply is removed during operation and then

re-applied before the power-on-reset signal has been reset,

the part will remain latched off. A solution for this problem is

shown in

Figure 6, using a voltage divider of 4:5 ratio to pull

the SD pin up to VLIN5. With the voltage divider, the SD pin

always falls below the logic low level and executes the

power-on-reset after VIN drops below 3V. External shudown

control is included as an option.

Dual-Phase Parallel Outputs

In applications with high output current demand, the two

switching channels can be configured to operate as a

two-phase converter to provide a single output voltage with

current sharing between the two switching channels. This

approach greatly reduces the stress and heat on the output

stage components while lowering input ripple current.

Figure

7 shows a typical example for the two-phase operation.

Because precision current sense is the primary design crite-

ria to ensure accurate current sharing between the two

channels, both channels must use external sense resistors

for current sensing. To minimize the error between the error

amplifiers of the two channel, tie the feedback pins FB1_FIX

and FB2_FIX together and connect to one voltage divider for

output voltage sensing. Also, tie the COMP1 and COMP2

together and connect to the compensation network. Since

there is only one output involved, POOGD1 and 2, and VO1

and 2 should be connected in pairs for monitoring the single

output rail. ON1 and ON2 should be tied together to enable

and disable both channels simultaneously.

20015925

FIGURE 3. Connecting OUT3 to VLIN5 when not in use

20015924

FIGURE 4. Connecting LDOFB to VLIN5 to disable the

LDODRV and the UVP associated with it

20015926

FIGURE 5. Adding a resistor in series with the CBOOT

pin to suppress the turn-on switching noise

20015927

FIGURE 6. Voltage divider ratio for SD pin

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