TABLE 1. Shut Down Latch Truth Table

Input

Output

ovp1

ovp2

uvp1

uvp2

uvp4

oc3

ch1 on

ch2 on

fault

ssto1

ssto2

uv_delay

latch off

11

0

1

11

0

1

1

1

0

1

cap

1

1

1

0

1

cap

1

1

1

0

1

cap

1

000001

000

cap

0

All other combinations

0

Notes:

1.

’fault’ is the logic OR of UVLO and thermal shutdown.

2.

’cap’ means the pin has a capacitor of appropriate value between it and ground.

3.

Positive logic is used.

4.

ssto1, ssto2 means soft start timeout for Ch 1 and Ch 2 respectively.

5.

A blank value means ’don’t care’.

6.

″oc3″ means OUT3 output current over 100mA current.

7.

″uvp4″ means UVP of the linear regulated output controlled by LDODRV.

8.

SD pin is pulled high.

TABLE 2. Power Good Truth Table

Input

Output

ovp1

ovp2

uvpg1

uvpg2

uvpg4

ch1 on

ch2 on

fault

latch

off

SD

PGOOD1

PGOOD2

1

1

1

100

1

1

1

100

11

1

0

11

1

0

001

10

0

1

1

01

0

01

0

00

10

0

1

1

0

0

100

1

1

1

100

1

100

000

Notes:

1.

Positive logic is used.

2.

A blank value means ’don’t care’.

3.

The symbol uvpg1, 2, 4 means the power good undervoltage threshold of the corresponding channel.

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