LM2645 datasheet(3/20 Pages) NSC

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Pin Descriptions (Continued)

of the top MOSFET or the voltage across an external current

sense resistor to determine if an over-current condition has

occurred in Channel 2.

RSNS2 (Pin 26): The negative (−) Kelvin sense for the

internal current limit comparator of Channel 2. Always use a

separate trace to connect this pin to the current sense point.

Connect this pin to the low side of the current sense resistor

that is placed between V

IN and the drain of the top MOSFET.

When the Vds of the top MOSFET is used for current sens-

ing, then connect this pin to the source of the top MOSFET.

KS2 (Pin 27): The positive (+) Kelvin sense for the internal

current limit comparator of Channel 2. Use a separate trace

to connect this pin to the current sense point. Connect to Vin

as close to the node of the current sense resistor; when no

current-sense resistor is used, connect it as close to the

Drain node of the upper MOSFET.

SW2 (Pin 28): : Switch-node connection for Channel 2,

which is connected to the source of the top MOSFET. It

serves as the negative supply rail for the topside gate driver,

HDRV2.

HDRV2 (Pin 29): Top-side gate-drive output for Channel 2. A

floating drive output that rides on the switching-node voltage.

CBOOT2 (Pin 30): Bootstrap capacitor connection. It serves

as the positive supply rail for the Channel 2 top-side gate

drive.

VDD2 (Pin 31): The supply rail for the Channel 2 low-side

gate drive, usually ties together with VDD1. Connect to

VLIN5 through a 4.7

Ω resistor and bypassed to ground with

a ceramic capacitor of at least 1µF.

LDRV2 (Pins 32, 33): Low-side gate-drive output for Chan-

nel 2. Tie these two pins together.

PGND2 (Pin 34): Power ground for Channel 2.

OUT3 (Pin 35): The fixed 3.3V linear regulated output. De-

rived from VLIN5 by an internal LDO, it is current limited at

100mA. The continuous output current is a function of the

ambient operating temperature and the total power dissipa-

tion in the chip and must be derated accordingly. See (Note

2) in Electrical Characteristics section.

EXT (Pin 36): External power input to an internal switch.

This pin is usually connected to the fixed 5V output of

Channel 1. When the voltage on this pin is higher than 4.7V,

the internal 5V LDO that provides VLIN5 from VIN is dis-

abled, and an internal switch connects VLIN5 to this pin to

minimize dissipation in the chip. Connect this pin to ground

and VLIN5 to VIN if VIN is operating in 4.5V to 5.5V range.

VLIN5 (Pin 37): This pin is the output of an internal 5V LDO

regulator derived from VIN when no external 5V supply is

available. It supplies the internal bias for the chip, supplies

the boostrap circuitry for gate drive and serves as the input

supply of an internal LDO to generate OUT3. Bypass this pin

to power ground with a minimum of 4.7µF ceramic capacitor.

Connect this pin to the VIN pin when Vin is operating in 4.5V

to 5.5V range.

VIN (Pin 38):The input power of the chip. Connects to the

upper (+) input rail of the system.

PGND1 (Pin 39):Power ground for Channel 1.

LDRV1 (Pins 40, 41): Low-side gate-drive output for Chan-

nel 1. Tie these two pins together.

VDD1 (Pin 42): The supply rail for the low-side gate drive of

Channel 1. Same function as VDD2 (Pin 31).

CBOOT1 (Pin 43): Bootstrap capacitor connection. It serves

as the positive supply rail for the Channel 1 top-side gate

drive.

HDRV1 (Pin 44): Top-side gate-drive output for Channel 1.

See HDRV2 (Pin 29).

SW1 (Pin 45): Switch-node connection for Channel 1, See

SW2 (Pin 28).

KS1 (Pin 46): The upper (+) Kelvin sense for the internal

current limit comparator of Channel 1 (see KS2, Pin 27).

RSNS1 (Pin 47): The lower (−) Kelvin sense for the internal

current limit comparator of Channel 1 (see RSNS2, Pin 26).

ILIM1 (Pin 48): Current limit threshold setting for Channel 1

(see ILIM2, Pin 25).

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