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CS61535A датащи(PDF) 19 Page - Cirrus Logic |
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CS61535A датащи(HTML) 19 Page - Cirrus Logic |
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19 / 48 page ![]() impedance state either after bit D7 is output or at the end of the hold period of data bit D7. An address/command byte, shown in Table 7, precedes a data register. The first bit of the ad- dress/command byte determines whether a read or a write is requested. The next six bits contain the address. The CS61535A responds to address 16 (0010000). The last bit is ignored. The data register, shown in Table 8, can be writ- ten to the serial port. Data is input on the eight clock cycles immediately following the ad- dress/command byte. Bits 0 and 1 are used to clear an interrupt issued from the INT pin, which occurs in response to a loss of signal or a problem with the output driver. If bits 0 or 1 are true, the corresponding interrupt is suppressed. So if a loss of signal interrupt is cleared by writing a 1 to bit 0, the interrupt will be reenabled by writing a 0 to bit 0. This holds for DPM as well. Writing a "1" to either "Clear LOS" or "Clear DPM" over the serial interface has three effects: 1) the current interrupt on the serial interface will be cleared. (Note that simply reading the register bits will not clear the interrupt), 2) output data bits 5, 6 and 7 will be reset as appropriate, 3) future interrupts for the corresponding LOS or DPM will be prevented from occuring). Writing a "0" to either "Clear LOS" or "Clear DPM" enables the corresponding interrupt for LOS or DPM. Output data from the serial interface is presented as shown in Tables 9 and 10. Bits 2, 3 and 4 can be read to verify line length selection. Bits 5, 6 and 7 must be decoded. Codes 101, 110 and 111 (bits 5, 6 and 7) indicate LOS and DPM state changes. Writing a "1" to the "Clear LOS" and/or "Clear DPM" bits in the register also resets status bits 5, 6, and 7. SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in appli- cations where the host proc esso r has a bidirectional I/O port. LSB: first bit in 0 clr LOS Clear Loss of Signal 1 clr DPM Clear Driver Performance Monitor 2 LEN0 Bit 0 - Line Length Select 3 LEN1 Bit 1 - Line Length Select 4 LEN2 Bit 2 - Line Lenght Select 5 RLOOP Remote Loopback 6 LLOOP Local Loopback MSB: last bit in 7 TAOS Transmit All Ones Select Table 8. Input Data Register LSB: first bit in 0 LOS Loss of Signal 1 DPM Driver Performance Monitor 2 LEN0 Bit 0 - Line Length Select 3 LEN1 Bit 1 - Line Length Select 4 LEN2 Bit 2 - Line Lenght Select Table 9. Output Data Bits 0 - 4 Bits Status 56 7 000 Reset has occurred or no program input. 001 TAOS in effect. 010 LLOOP in effect. 011 TAOS/LLOOP in effect. 100 RLOOP in effect 101 DPM changed state since last "clear DPM" occured. 110 LOS changed state since last "clear LOS" occured. 111 LOS and DPM have changed state since last "clear LOS" and "clear DPM". Table 10. Coding for Serial Output Bits 5, 6, 7 CS61535A DS40F2 19 |
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