CS61535A datasheet(16/48 Pages) CIRRUS

16 / 48 page

period will be 648 ns. Similar calculations hold

for the E1 rate.

The clock recovery circuit is designed to accept at

least 0.4 UI of jitter at the receiver. Since the data

stream contains information only when ones are

transmitted, a clock/data recovery circuit must as-

sume a zero when no signal is measured during a

bit period. Likewise, when zeros are received, no

information is present to update the clock recov-

ery circuit regarding the trend of a signal which is

jittered. The result is that two ones that are sepa-

rated by a string of zeros can exhibit maximum

deviation in pulse arrival time. For example, one

half of a period of jitter at 100 kHz occurs in 5

µs, which is 7.7 T1 bit periods. If the jitter ampli-

tude is 0.4 UI, then a one preceded by seven zeros

can have maximum displacement in arrival time,

i.e. either 0.4 UI too early or 0.4 UI too late. For

the CS61535A, the data recovery circuit correctly

assigns a received bit to its proper clock period if

it is displaced by less than 6/13 of a bit period

from its optimal location. Theoretically, this

would give a jitter tolerance of 0.46 UI. The ac-

tual jitter tolerance of the CS61535A is only

slightly less than the ideal.

In the event of a maximum jitter hit, the RCLK

clock period immediately adjusts to align itself

with the incoming data and prepare to accurately

place the next one, whether it arrives one period

later, or after another string of zeros and is dis-

placed by jitter. For a maximum early jitter hit,

RCLK will have a period of 7/13 * 648 ns = 349

ns (2,865,961 Hz). For a maximum late jitter hit,

RCLK will have a period of 19/13 * 648 ns = 947

ns (1,055,880 Hz).

Loss of Signal

Receiver loss of signal is indicated upon receiv-

ing 175 consecutive zeros. A digital counter

counts received zeros based on RCLK cycles. A

zero input is determined either when zeros are re-

ceived, or when the received signal amplitude

drops below a 0.3 V peak threshold.

The receiver reports loss of signal by setting the

Loss of Signal pin, LOS, high. If the serial inter-

face is used, the LOS bit will be set and an

interrupt issued on INT. LOS will go low (and

flag the INT pin again if serial I/O is used) when

a valid signal is detected. Note that in the Host

Mode, LOS is simultaneously available from both

the register and pin 12.

In a loss of signal state, the RCLK frequency will

be equal to the ACLKI frequency since ACLKI is

being used to calibrate the clock recovery circuit.

Received data is output on RPOS and RNEG (or

RDATA) regardless of LOS status. The LOS re-

turns to logic zero when the ones density reaches

12.5% (based upon 175 bit periods staring with a

one and containing less than 100 consecutive ze-

ros) as prescribed in ANSI T1.231-1993. A

power-up or manual reset will also set LOS high.

Local Loopback

The local loopback mode takes clock and data

presented on TCLK, TPOS, and TNEG (or

TDATA) and outputs it at RCLK, RPOS and

RNEG (or RDATA). Local loopback is selected

by taking pin 27 high, or LLOOP may be selected

using the serial interface. The data on the trans-

mitter inputs is transmitted on the line unless

TAOS is selected to cause the transmission of an

all ones signal instead. Receiver inputs are ig-

nored when local loopback is in effect. The jitter

attenuator is not included in the local loopback

data path. Selection of local loopback overrides

the chip’s loss of signal response.

Remote Loopback

In remote loopback, the recovered clock and data

input on RTIP and RRING are sent through the

jitter attenuator and back out on the line via TTIP

and TRING. The recovered incoming signals are

also sent to RCLK, RPOS and RNEG (or

CS61535A

DS40F2

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