DS2155 datasheet(48/262 Pages) DALLAS

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DS2156

48 of 262

6.1

Power-Up Sequence

The DS2156 contains an on-chip power-up reset function that automatically clears the writeable register

space immediately after power is supplied to the DS2156. The user can issue a chip reset at any time.

Issuing a reset disrupts traffic flowing through the DS2156 until the device is reprogrammed. The reset

can be issued through hardware using the TSTRST pin or through software using the SFTRST function in

the master mode register. The LIRST (LIC2.6) should be toggled from 0 to 1 to reset the line interface

circuitry. (It takes the DS2156 about 40ms to recover from the LIRST bit being toggled.) Finally, after the

TSYSCLK and RSYSCLK inputs are stable, the receive and transmit elastic stores should be reset (this

step can be skipped if the elastic stores are disabled).

6.1.1 Master Mode Register

MSTRREG

Master Mode Register

00h

Bit #

Name

—

URST

TEST1

TEST0

T1/E1

SFTRST

Default

Bit 0/Software-Issued Reset (SFTRST). A 0-to-1 transition causes the register space in the DS2156 to be cleared.

A reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed.

Bit 1/DS2156 Operating Mode (T1/E1). Used to select the operating mode of the framer/formatter (digital)

portion of the 2156. The operating mode of the LIU must also be programmed.

0 = T1 operation

1 = E1 operation

Bits 2, 3/Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the DS2156 into

known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to

isolate devices from shared buses.

TEST1

TEST0

Effect On Output Pins

Operate normally

Force all output pins into three-state (including all I/O pins and parallel port

pins)

Force all output pins low (including all I/O pins except parallel port pins)

Force all output pins high (including all I/O pins except parallel port pins)

Bit 4/UTOPIA Reset (URST). A 0-to-1 transition causes the UTOPIA interface to reset.

Bits 5 to 7/Unused, must be set to 0 for proper operation

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