DS2155 datasheet(90/262 Pages) DALLAS

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DS2156

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15.1.2

Hardware-Based Receive Signaling

In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin.

RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The

signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSER. The

signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted

into the original data stream in a different alignment that is determined by a multiframe signal from the

RSYNC pin. In this mode, the receive elastic store can be enabled or disabled. If the receive elastic store

is enabled, then the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF

framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The

RSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the

AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6

contain the same data as bits 7 and 8, respectively, in each channel. The RSIG data is updated once a

multiframe (1.5ms) unless a freeze is in effect. See the timing diagrams in Section 34 for some examples.

15.1.2.1

Receive Signaling Reinsertion at RSER

In this mode, the user provides a multiframe sync at the RSYNC pin and the signaling data is reinserted

based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data

stream, the original signaling data and the realigned data. This is of little consequence in voice channels.

Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. In this

mode, the elastic store must be enabled; however, the backplane clock can be either 1.544MHz or

2.048MHz.

Signaling reinsertion can be enabled on a per-channel basis by setting the RSRCS bit high in the PCPR

registers for T1 mode and PCDR1–PCDR4 registers for E1 mode. In E1 mode, the user generally selects

all channels or none for reinsertion. In E1 mode, signaling reinsertion on all channels can be enabled with

a single bit, SIGCR.7 (GRSRE). This bit allows the user to reinsert all signaling channels without having

to program all channels through the per-channel function.

15.1.2.2

Force Receive Signaling All Ones

In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to a 1 by

using the per-channel register (Section 5). The user sets the BTCS bit in the PCPR register. The channels

that will be forced to 1 are selected by writing to the PCDR1–PCDR3 registers.

15.1.2.3

Receive Signaling Freeze

The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a

loss of synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of

BellCore TR–TSY–000170 for signaling freezing. To allow this freeze action to occur, the RFE control

bit (SIGCR.4) should be set high. The user can force a freeze by setting the RFF control bit (SIGCR.3)

high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe

buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER

pin if receive signaling reinsertion is enabled). When freezing is enabled (RFE = 1), the signaling data is

held in the last-known good state until the corrupting error condition subsides. When the error condition

subsides, the signaling data is held in the old state for at least an additional 9ms (or 4.5ms in D4 framing

mode) before updating with new signaling data.

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