DS2155 datasheet(9/262 Pages) DALLAS

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DS2156

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§ Flexible signaling support

–

Software or hardware based

–

Interrupt generated on change of signaling data

–

Receive signaling freeze on loss-of-sync,

carrier loss, or frame slip

§ Addition of hardware pins to indicate carrier loss

and signaling freeze

§ Automatic RAI generation to ETS 300 011

specifications

§ Access to Sa and Si bits

§ Option to extend carrier loss criteria to a 1ms

period as per ETS 300 233

§ Japanese J1 support

–

Ability to calculate and check CRC6 according

to the Japanese standard

–

Ability to generate Yellow Alarm according to

the Japanese standard

TDM Bus

§ Dual two-frame independent receive and transmit

elastic stores

–

Independent control and clocking

–

Controlled slip capability with status

–

Minimum delay mode supported

§ 16.384MHz maximum backplane burst rate

§ Supports T1 to CEPT (E1) conversion

§ Programmable output clocks for fractional T1, E1,

H0, and H12 applications

§ Interleaving PCM bus operation

§ Hardware signaling capability

–

Receive signaling reinsertion to a backplane

multiframe sync

–

Availability of signaling in a separate PCM

data stream

–

Signaling freezing

§ Ability to pass the T1 F-bit position through the

elastic stores in the 2.048MHz backplane mode

§ Access to the data streams in between the

framer/formatter and the elastic stores

§ User-selectable synthesized clock output

UTOPIA Bus

§ Supports fractional T1/E1 and arbitrary bit rates in

multiples of 64kbps (DS0/TS) up to 2.048Mbps

§ Supports clear E1

§ Compliant to the ATM forum specifications for

ATM over DS1 and E1, respectively

§ Standard UTOPIA-II interface to the ATM layer

§ Configurable UTOPIA address

§ Supports diagnostic loopback

§ Optional payload scrambling in transmit direction

and descrambling in receive direction as per the

ITU I.432 for the cell-based physical layer

§ Optional HEC insertion in transmit direction with

programmable COSET polynomial addition

§ Option of using either idle or unassigned cells for

cell-rate decoupling in transmit direction

§ 1-Byte programmable pattern for payload of cells

used for cell-rate decoupling

§ Transmit FIFO depth configurable to either 2, 3, 4

cell deep, which provides control over cell latency

§ Transmit FIFO depth indication for 2-cell space

§ Optional single-bit HEC error insertion

§ HEC-based cell delineation

§ Optional single-bit HEC error correction in the

receive direction

§ Optional filtering of HEC errored cells received

§ Optional receive idle/unassigned cell filtering

§ Programmable loss-of-cell delineation (LCD)

integration and optional interrupt

§ Interrupt for FIFO overrun in receive direction

§ Saturating counts for:

–

Number of error-free assigned cells received

and transmitted

–

Number of correctable and uncorrectable HEC-

errored cells received

§ Optional internally generated clock (system clock

divided by 8) in diagnostic loopback mode

HDLC Controllers

§ Two independent HDLC controllers

§ Fast load and unload features for FIFOs

§ SS7 support for FISU transmit and receive

§ Independent 128-byte Rx and Tx buffers with

interrupt support

§ Access FDL, Sa, or single/multiple DS0 channels

§ DS0 access includes Nx64 or Nx56

§ Compatible with polled or interrupt driven

environments

§ Bit-oriented code (BOC) support

Test and Diagnostics

§ Programmable on-chip bit error-rate testing

§ Pseudorandom patterns including QRSS

§ User-defined repetitive patterns

§ Daly pattern

§ Error insertion single and continuous

§ Total bit and errored bit counts

§ Payload error insertion

§ Error insertion in the payload portion of the T1

frame in the transmit path

§ Errors can be inserted over the entire frame or

selected channels

§ Insertion options include continuous and absolute

number with selectable insertion rates

§ F-bit corruption for line testing

§ Loopbacks: remote, local, analog, and per-channel

loopback

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