HV7321 datasheet(19/30 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005639A-page 19

HV7321

4.0

DEVICE DESCRIPTION

4.1

Overview

The HV7321 is a 4-channel, 5-level ultrasound

transmitter with built-in T/R switches, output protection

diodes and clamp diodes.

The HV7321 can provide up to

2.6A and the output

voltage swing can be up to

80V.

The HV7321 supports both Transparent and Re-Timing

mode. The re-timing clock frequency can support up

to 220 MHz. The re-timing feature helps reduce the

output jitter introduced by the driving FPGA.

4.2

Recommended Power-up

Sequence

Powering up/down in any arbitrary sequence will not

cause any damage to the device. The powering-up

sequences in Table 4-1 are only recommended in order

to minimize possible in-rush current. Figure 4-1 shows

the timing diagram of related signals.

FIGURE 4-1:

Power-On Events and Power-Saving Time Diagram.

4.3

Operation Modes

There are five modes of operation: Device Disabled,

Output Disabled, Pulsed-Echo Mode, CW Mode-0 and

CW Mode-1.

4.3.1

DEVICE ENABLE MODE

In Device Disabled mode, the regulators are turned off

when REN is low. The regulators are ON when

REN = VLL. All regulators are ON except VNEG and

VPOS for power saving when REN = 1. When REN is

low, OEN = X (OEN = 1 or 0) since device is disabled.

Refer to Table 4-2.

4.3.2

OUTPUT HIGH Z MODE

In Output Disabled mode, regulators are enabled

REN = 1 and OEN = 0 (Output Enable logic input) and

output pins (TX0-3) are in high Z state. OEN = 1

enables the outputs.

4.3.3

PULSED-ECHO MODE

Pulsed-Echo mode (B-mode) enables the 5-level

waveform generation. OEN = 1, MODE = 0, and PWS =

1 enable Pulsed-Echo mode after HV7321 powers on.

SEL/NEG/POS inputs of desired channel determine

the corresponding TX Output pulse.

TABLE 4-1:

POWER-UP SEQUENCE

Step

Power-Up Description

1VLL ON with logic signal low

2VDD, VGP and VGN ON

3REN = 1

4VPP0,1 and VNN0,1 ON

OEN = 1 & Logic control signal active

PGD internal

VCPOS output

VLL input

VDD input

VDD > VDDUVON

VGP input

VPP input

OEN input

REN input

Internal VDD Power-Good Signal

|VGN|

|VNN|

tOEN_ON

VCNEG output

VPP

VCPF

VCNF

VNN

(3V)

Ready to Work

(Power Saving)

TABLE 4-2:

REN & OEN LOGIC INPUTS

REN

OEN

Device

TX Output

Disabled

high Z

Enabled

high Z

Enabled

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