MCP3909-ESLASHSS datasheet(33/44 Pages) MICROCHIP

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 2006-2012 Microchip Technology Inc.

DS22025C-page 33

MCP3909

6.2

Achieving Line Cycle Sampling

with Zero Blind Cycles

In most energy meter applications, it will be necessary

to have 2N samples for each 50 or 60 Hz line cycle,

where N is typically 64, 128 or 256. Controlling the

MCLK of the MCP3909 allows you to control the sam-

ple rate and ultimately the data ready (DR) pulses for

coherent waveform sampling.

The following scheme shows how the TIMER and

COMPARATOR modules of the PIC MCU can be used

to generate the clock for the MCP3909 from either a

PLL internal MCLK. For class 0.2 or class 0.1 meter

designs that require harmonic analysis using a PLL is

recommended to shift sample rate with line cycle drift,

e.g. line cycle changes from 60 Hz to 59.1 Hz. This is

shown as option 1 in Figure 6-2.

A simpler lower cost option would be to choose a fre-

quency that would give an integer number of line cycles

for exactly 50 Hz (or 60 Hz). This is possible using a

39.3216 MHz crystal for the PIC18F device.

Figure 6-2 shows example clock frequencies to

achieve 128 samples for each line cycle, 1.63 MHz for

a 50 Hz line, or 1.96 MHz for a 60 Hz line. The

MCP3909 clock can operate from 1 MHz to 4 MHz.

Using this approach, the PIC MCU can gather the

waveform data immediately after the data ready pulse,

at up to 10 MHz. The remainder of the time can be used

to calculate the power measurements to achieve true

line cycle sampling with zero blind cycles.

For more information and firmware, see the Microchip

web page for demo board information.

FIGURE 6-2:

Using the PIC device to control the MCP3909 MCLK to achieve 2N samples per line

cycle, 3-phase sampling shown with 6 ADCs.

50 (or 60 Hz)

PLL Circuit

x 32768

Phase A || B || C

MCP3909

39.3216 MHz

PIC MCU

CCP2 / 32768

(50 or 60 Hz)

tSAMPLE

tLINE_CYC

SDO DR

Phase A,B,C I & V Data

16 bits

tSAMPLE

IRQ

Option 1

Option 2

1.63 MHz (50)

3.579 MHz

MCLK input

DR Pulse

To PIC MCU

IRQ

1.96 MHz (60)

x 6 ADCs

128 samples/line cycle

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