MCP3909-ESLASHSS datasheet(20/44 Pages) MICROCHIP

20 / 44 page

MCP3909

DS22025C-page 20

 2006-2012 Microchip Technology Inc.

4.4

Ultra-Low Drift VREF

The MCP3909 contains an internal voltage reference

source specially designed to minimize drift over tem-

perature. This internal VREF supplies reference voltage

to both current and voltage channels ADCs. The typical

value of this voltage reference is 2.4V ±100 mV. The

internal reference has a very low typical temperature

coefficient of ±15 ppm/°C, allowing the output frequen-

cies to have minimal variation with respect to tempera-

ture since they are proportional to (1/VREF)².

The output pin for the voltage reference is REFIN/OUT.

Appropriate bypass capacitors must be connected to

the

REFIN/OUT

for

proper

operation

(see Section 6.0 “Applications Information”). The

voltage reference source impedance is typically 4 kΩ



which enables this voltage reference to be overdriven

by an external voltage reference source.

If an external voltage reference source is connected to

the REFIN/OUT pin, the external voltage will be used

as the reference for both current and voltage channel

ADCs. The voltage across the source resistor will then

be the difference between the internal and external

voltage. The allowed input range for the external volt-

age source goes from 2.2V to 2.6V for accurate mea-

surement error. A VREF value outside of this range will

cause additional heating and power consumption due

to the source resistor, which might affect measurement

error.

4.5

Power-On Reset (POR)

The MCP3909 contains an internal POR circuit that

monitors analog supply voltage AVDD during operation.

This circuit ensures correct device startup at system

power-up and system power-down events. The POR

circuit has built-in hysteresis and a timer to give a high

degree of immunity to potential ripple and noise on the

power supplies, allowing proper settling of the power

supply during power-up. A 0.1 µF decoupling capacitor

should be mounted as close as possible to the

AVDD pin, providing additional transient immunity

(see Section 6.0 “Applications Information”).

The threshold voltage is typically set at 4V, with a toler-

ance of about ±5%. If the supply voltage falls below this

threshold, the MCP3909 will be held in a Reset condi-

tion (equivalent to applying logic ‘0’ on the MCLR pin).

The typical hysteresis value is approximately 200 mV

in order to prevent glitches on the power supply.

Once a power-up event has occurred, an internal timer

prevents the part from outputting any pulse for approx-

imately 1s (with MCLK = 3.58 MHz), thereby prevent-

ing potential metastability due to intermittent resets

caused by an unsettled regulated power supply.

Figure 4-3 illustrates the different conditions for a

power-up and a power-down event in the typical

conditions.

FIGURE 4-3:

Power-On Reset Operation.

4.6

High-Pass Filters and Multiplier

The active real-power value is extracted from the DC

instantaneous power. Therefore, any DC offset compo-

nent present on Channel 0 and Channel 1 affects the

DC component of the instantaneous power and will

cause the real-power calculation to be erroneous. In

order to remove DC offset components from the instan-

taneous power signal, a high-pass filter has been intro-

duced on each channel. Since the high-pass filtering

introduces phase delay, identical high-pass filters are

implemented on both channels. The filters are clocked

by the same digital signal, ensuring a phase difference

between the two channels of less than one MCLK

period. Under typical conditions (MCLK = 3.58 MHz),

this phase difference is less than 0.005°, with a line fre-

quency of 50 Hz. The cut-off frequency of the filter

(4.45 Hz) has been chosen to induce minimal gain

error at typical line frequencies, allowing sufficient set-

tling time for the desired applications. The two high-

pass filters can be disabled by applying logic ‘0’ to the

HPF pin.

FIGURE 4-4:

HPF Magnitude Response

(MCLK = 3.58 MHz).

AVDD

4.2V

DEVICE

MODE

RESET

PROPER

OPERATION

RESET

PULSE

OUT

Time

-40

-35

-30

-25

-20

-15

-10

-5

0.1

100

1000

Frequency (Hz)

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