CS9211 datasheet(30/62 Pages) NSC

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Revision 2.1

Functional Description (Continued)

Figure 3-10 shows the order in which pixels will be dithered

down to the next available intensity, as the least significant

bits increase from “0”, for 1-, 2-, 3-, and 4-bit dithering.

The values are given in hexadecimal. The CS9211 also

supports 5-bit dithering but that pattern is not shown.

The patterns shown in Figure 3-10 are stored in the

CS9211’s internal ROM. These patterns will be used when

the dither ROM is selected by Offset 40Ch[12] = 0.

3.2.6.3

Controlling Dithering

Table3-13"DitheringProgramming Bits"onpage32indi-

cates the register settings used to control the dithering pro-

cess.

The incoming pixel data goes through the dithering logic.

Dither logic is enabled by writing a “1” to Offset 40Ch[0]. If

the dithering logic is disabled, then only FRM will be pro-

ducing the color intensities. FRM cannot be turned off.

The first step in setting the registers is to decide how to

split the incoming bits per pixel between bits used for FRM

and bits used for dithering. Offset 40Ch[6:4, 3:1] deter-

mines these settings; these two groups of bits must be set

to match each other.

Next, the user must decide whether to use the pre-pro-

grammed (ROM) internal dithering patterns or create new

ones in the dither RAM. If RAM will be used, program Off-

set 40Ch[12] and Offset 424h[7:6] accordingly. If pre-pro-

grammed dither patterns (ROM) will be used, the dither

RAM will go into a reduced power state when it is de-

selected by Offset 40Ch[12] = 0 and Offset 424h[7:6] = 00.

Figure 3-10. N-Bit Dithering Pattern Schemes

193

473

222

111

4-Bit Scheme

3-Bit Scheme

2-Bit Scheme

1-Bit Scheme

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