CS9211 datasheet(24/62 Pages) NSC

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Revision 2.1

Functional Description (Continued)

Frame Pulse (VSYNC)

VSYNC pulses are provided to the attached panel in one of

two ways, either externally or internally. If the PASS_THRU

mode is set (Offset 404h[30] = 1), the input FP_VSYNC

(pin 99) is passed through unchanged to the output pin

FLM/VSYNC (pin 33).

If the PASS-THRU mode is not set (Offset 404h[30] = 0),

then the VSYNC/FLM pulse is generated internally in

response to the input FP_VSYNC pulse. The manner in

which the internal VSYNC/FLM pulse is generated

depends on the mode set by Offset 404h[21:16].

If an SSTN panel is chosen, then the output FLM pulse is

generated in response to each incoming FP_VSYNC.

If a DSTN panel is chosen, then the counter VPAN_SIZE

(Offset 400h[26:16]) comes into play (see Table 3-8). The

first FLM (First Line Marker) is generated at the beginning

of the first line. Then the CS9211 counts the number of

lines. A second FLM is generated when half number of total

lines has been reached. This is required because in DSTN

panels, both halves of the panel are receiving new lines of

data simultaneously, thus a new FLM pulse is required

when both halves of the panel have been simultaneously

refreshed.

The polarity of the output VSYNC pulse may be inverted by

Offset 404h[23] only if Offset 404h[24] = 1.

Shift Clock

Table 3-7 shows the relationship between the output shift

clock (SHFCLK) and the input DOTCLK. This relationship

varies depending on the panel type as selected by Offset

404h[21:18].

One additional bit exists to allow more control over the out-

put shift clock. The Panel Shift Clock Retrace Activity Con-

trol bit at Offset 404h[27] allows the shift clock to be active

only during active data transfer or free running as required

by some panel types. In case of STN (DSTN/SSTN)

modes, the panel shift clock retrace activity control bit does

not have any effect.

Table 3-7. Input DOTCLK vs. Panel SHFCLK

Panel

Clock

DSTN

24-Bit

DSTN

16-Bit

STN

8-Bit

TFT

9-Bit

TFT

18-Bit

TFT

9+9-Bit

TFT

12+12-Bit

SHFCLK

DOTCLK/4

DOTCLK/(3:2:3)

DOTCLK

DOTCLK/2

Table 3-8. Panel Output Timing Selection Bits

Bit

Name

Description

Offset 400h-403h

Panel Timing Register 1 (R/W)

Reset Value = 0000000h

FP_HSYNC_POL

FP_HSYNC Input Polarity: Selects positive or negative polarity of the FP_HSYNC input (pin 97).

Program this bit to match the polarity of the incoming FP_HSYNC signal. Note that bit 22 of Offset

404h independently controls the polarity of the output HSYNC.

0 = FP_HSYNC is normally low, transitioning high during sync interval (Default).

1 = FP_HSYNC is normally high, transitioning low during sync interval.

26:16

PAN_VSIZE

Panel Vertical Size: This field represents the panel vertical size in terms of scan lines. The value

programmed should be equal to the panel size that is being connected.

This can be used only for DSTN/STN modes.

Example: 640x480 = 1E0h, 800x600 = 258h, and 1024x768 = 300h.

7:5

HSYNC_LEADING_

EDGE

Horizontal Sync Leading Edge Position: Selects the position of the leading edge of the output

HSYNC pulse with respect to the rising edge of the modified input HSYNC pulse. The modified input

HSYNC pulse is that which has been inverted, or not inverted, by bit 29. The position is programma-

ble in steps of 1 DOTCLK, starting at 2 DOTCLOCKS and extending up to 8. Bit 27 must be set in

order for bits [7:5] to be recognized. Note that there are combinations of bits [7:5] and [4:0] that can

result in a zero- or negative-length pulse, for example if the trailing edge is positioned before the

leading edge. In this case, the output pulse will not be generated.

000 = No delay from the input HSYNC (Default).

001-111 = Position the HSYNC leading edge by 2 to 8 DOTCLKs with respect to the input HSYNC

rising edge. Note that there is no setting for a position of 1 DOTCLOCK.

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