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ST92196A датащи(PDF) 113 Page - STMicroelectronics

номер детали ST92196A
подробное описание детали  8/16-BIT MCU FOR TV APPLICATIONS WITH UP TO 96K ROM, ON-SCREEN-DISPLAY AND 1 OR 2 DATA SLICERS
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- OSDRAM CONTROLLER
OSDRAM CONTROLLER (Cont’d)
8.4.3 OSDRAM Controller Reset Configuration
During and after a reset, the OSDRAM access is
disabled.
When the OSDRAM controller is software disa-
bled, it will:
1. Complete the current slot.
2. Complete any pending write operation (a few
slots may elapse).
3. Switch off any OSDRAM interface activity.
8.4.3.1 OSDRAM Controller Running Modes
2 control bits called “OSDE” (OSD Enable) and
“DION” (Display ON) are used to enable the OS-
DRAM controller. Both are also shared by the Dis-
play controller.
These 2 bits are located in the OSDER register.
This register is described in the On Screen Display
Controller Chapter.
8.4.3.2 CPU Slowdown on OSDRAM access
As described above, the OSDRAM controller puts
priority on TV real time constraints and may slow-
down the CPU (through “wait” cycle insertion)
when any OSDRAM access is requested. The ef-
fective duration of the CPU slowdown is a complex
function of the OSDRAM controller working mode
and of the respective PIXCLK frequency (OS-
DRAM frequency) and the Core INTCLK frequen-
cy.
8.4.3.3 OSDRAM Mapping
The OSDRAM is mapped in the memory space,
segment 22h, starting from address 0000h to ad-
dress 017Fh (384 bytes).
The OSDRAM mapping is described in the On
Screen Display Controller Chapter.



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