ST92196A datasheet(112/268 Pages) STMICROELECTRONICS

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- OSDRAM CONTROLLER

OSDRAM CONTROLLER (Cont’d)

8.4.2.1 Time Sharing during Display

The time necessary to display a character on the

screen defines the basic repetitive cycle of the OS-

DRAM controller. This whole cycle represents

therefore 18 clock periods. This cycle is divided in

9 sub-cycles called “slots”. Each slot is allocated in

real-time either to the CPU or the Display:

– In single mode, this 9-slot cycle is repeated con-

tinuously providing only CPU slots (single cycle),

until the OSDRAM controller is switched off by

the main program execution.

– In shared mode, this 9-slot cycle provides Dis-

play slots followed by CPU slots.

Each slot represents a two-byte exchange (read or

write) between the OSDRAM memory and the oth-

er units:

Display Reading slot (DIS): 16 bits are read from

the OSDRAM and sent to the display unit, the ad-

dress being defined by the display address gener-

ator.

Direct CPU Access slot (CPU): 16 bits are ex-

changed (read or write) between the OSDRAM

and its controller but only 8 bits are exchanged

with the CPU, the address being defined by the

CPU memory address bus.

Figure 51. Time Sharing during Display

Display reading is handled as follows:

– DIS(1) & DIS(2) are dedicated to reading the

character code, its parallel attributes & associat-

ed palette pointer.

– DIS(3) provides the foreground palette.

– DIS(4) provides the background palette. In case

of Underline activation (refer to the OSD control-

ler paragraph for more details), the DIS(4) slot is

no longer provides the background palette con-

tent (useless information) but recovers the Un-

derline color set data.

The CPU write accesses are handled as follows:

Because of the 16-bit word width inside the OS-

DRAM matrix, it is obviously necessary to perform

a CPU write access in 2 steps:

– Reading the OSDRAM word

– Rewriting it with the same values except for the

8 modified bits.

Each time a CPU write operation is started, the

next following CPU slot will be used as a read slot,

the effective write to the OSDRAM being complet-

ed at the next CPU slot.

8.4.2.2 Time Sharing within the TV line

At the beginning of each TV line, the OSDRAM is

accessed (read) by the Display controller in order

to get all the row attributes. When the TV line is

recognized as the one where data have to be dis-

played, the Shared cycle is activated at the time

the data has to be processed for display.

CPU

(R/W)

CPU

(R/W)

CPU

(R/W)

CPU

(R/W)

CPU

(R/W)

CPU

(R/W)

CPU

(R/W)

CPU

(R/W)

CPU

(R/W)

CPU

(R/W)

DIS

(1)

CPU

(R/W)

DIS

(2)

CPU

(R/W)

DIS

(3)

CPU

(R/W)

DIS

(4)

CPU

(R/W)

Shared Cycle

Single Cycle

One Character Display Time

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