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ST92196A датащи(PDF) 111 Page - STMicroelectronics |
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ST92196A датащи(HTML) 111 Page - STMicroelectronics |
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111 / 268 page ![]() 111/268 - OSDRAM CONTROLLER 8.4 OSDRAM CONTROLLER 8.4.1 Introduction The OSDRAM Controller handles the interface be- tween the Display Controller, the CPU and the OS- DRAM. The time slots are allocated to each unit in order to optimize the response time. The main features of the OSDRAM Controller are the following: s Memory mapped in Memory Space (segment 22h of the MMU) s DMA access for Display control s Direct CPU access 8.4.2 Functional Description The OSDRAM controller manages the data flows between the different sub-units (display controller, CPU) and the OSDRAM. A specific set of buses (16-bit data, 9-bit addresses) is dedicated to these data flows. The OSDRAM controller accesses these buses in real time. The OSDRAM controller has registers mapped in the ST9 register file. As this OSDRAM controller has also to deal with TV real time signals (On-Screen-Display), a spe- cific controller manages all exchanges: – Its timing generator uses the same frequency generator as the Display (Pixel frequency multi- plier), – Its controller can work in two TV modes: – Single mode: all time slots are dedicated to the CPU. – Shared mode: time slots are shared between the CPU and the Display. The shared mode is controlled by the Display controller. – Its architecture gives priority to the TV real time constraints: whenever there is access contention between the CPU and the Display (shared mode), the CPU is automatically forced in a “wait” configuration until its request is served. – Its controller enables a third operating mode (stand-alone mode) which allows the application to access the OSDRAM while the Display is turned off. In this case, the OSDRAM controller uses the CPU main clock. Figure 50. Display Architecture Overview 4 * 3 BITS DISPLAY CONTROLLER OSDRAM CONTROLLER OSD DISPLAY RAM CPU INTERFACE ROM FONT MATRIX REGISTER BUSES MEMORY BUSES ADDRESS (6+4 BITS) OSD ADDRESS (9 BITS) OSD DATA (16 BITS) RGB FB TRANSLUCENCY TSLU DATA (8 BITS) ADDRESS (22 BITS) DATA (8 BITS) |
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