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IS25LP080D датащи(PDF) 59 Page - Integrated Silicon Solution, Inc

номер детали IS25LP080D
подробное описание детали  SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  108 Pages
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производитель  ISSI [Integrated Silicon Solution, Inc]
домашняя страница  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP080D датащи(HTML) 59 Page - Integrated Silicon Solution, Inc

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IS25LP080D
IS25WP080D/040D/020D
Integrated Silicon Solution, Inc.- www.issi.com
59
Rev. A
09/02/2016
8.24 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h)
Set Read Parameter Bits
This device supports configurable burst length and dummy cycles in both SPI and QPI mode by setting three bits
(P2, P1, P0) and four bits (P6, P5, P4, P3) within the Read Register, respectively. To set those bits the SRPNV
and SRPV operation instruction are used. Details regarding burst length and dummy cycles can be found in Table
6.9, Table 6.10, and Table 6.11. HOLD#/RESET# pin selection (P7) bit in the Read Register can be set with the
SRPNV and SRPV operation as well, in order to select RESET# pin instead of HOLD# pin.
SRPNV is used to set the non-volatile Read register, while SRPV is used to set the volatile Read register.
Note: When SRPNV is executed, the volatile Read Register is set as well as the non-volatile Read Register.
Figure 8.40 Set Read Parameters Sequence In SPI Mode
Instruction = 65h or C0h/63h
CE #
SCK
SI
SO
Data In
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
7
3
2
1
0
6
5
4
High Impedence
Figure 8.41 Set Read Parameters Sequence In QPI Mode
65h or
C0h/63h
0
1
Mode 3
Mode 0
2
3
7:4
3:0
CE#
SCK
IO[3:0]
Data In



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