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IS25LP080D датащи(PDF) 53 Page - Integrated Silicon Solution, Inc |
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IS25LP080D датащи(HTML) 53 Page - Integrated Silicon Solution, Inc |
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53 / 108 page ![]() IS25LP080D IS25WP080D/040D/020D Integrated Silicon Solution, Inc.- www.issi.com 53 Rev. A 09/02/2016 8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h) Information Row Lock bits (IRL3~IRL0) can be set to “1” individually by WRFR instruction in order to lock Information Row. Since IRL bits are OTP, once it is set to “1”, it cannot set back to “0” again. Figure 8.32 Write Function Register Sequence In SPI Mode Instruction = 42h CE # SCK SI SO Data In 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3 Mode 0 7 3 2 1 0 6 5 4 High Impedence Figure 8.33 Write Function Register QPI Sequence In QPI Mode 42h 0 1 Mode 3 Mode 0 2 3 7:4 3:0 CE# SCK IO[3:0] Data In |
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