CAP1114 datasheet(58/102 Pages) MICROCHIP

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Multiple Channel Capacitive Touch Sensor and LED Driver

Datasheet

Revision 1.1 (02-04-11)

SMSC CAP1114

DATASHEET

6.21

Interrupt Enable Registers

The Interrupt Enable Registers determine whether a button press or GPIO input changing state causes

the interrupt pin to be asserted.

6.21.1

Interrupt Enable 1

Bit 7 - G_INT_EN - Enables the interrupt pin to be asserted if a slide, tap, or press and hold action is

detected on the grouped sensors.

‘0’ - The interrupt pin will not be asserted if a slide, tap, or press and hold action is detected on

the grouped sensors (associated with the UP, DOWN, TAP, and PH status bits).

‘1’ (default) - The interrupt pin will asserted if a slide, tap, or press and hold event is detected on

the grouped sensors (associated with the UP, DOWN, TAP, and PH status bits).

Bit 6 - S7_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS7 (associated

with the CS7 status bit).

‘0’ - The interrupt pin will not be asserted if a touch is detected on CS7 (associated with the CS7

status bit).

‘1’ (default) - The interrupt pin will be asserted is detected on CS7 (associated with the CS7 status

bit).

Bit 5 - S6_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS6 (associated

with the CS6 status bit).

Bit 4 - S5_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS5 (associated

with the CS5 status bit).

Bit 3 - S4_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS4 (associated

with the CS4 status bit).

Bit 2 - S3_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS3 (associated

with the CS3 status bit).

Bit 1 - S2_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS2 (associated

with the CS2 status bit).

Bit 0 - S1_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS1 (associated

with the CS1 status bit).

6.21.2

Interrupt Enable 2

These bits enable the interrupt pin to be asserted when the GPIOx status bit has been set.

Bit 7 - GPIO8_INT_EN - Enables the interrupt pin to be asserted if the GPIO8 status bit has been set.

‘0’ (default) - The interrupt pin will not be asserted if the GPIO8 status bit has been set.

‘1’ - The interrupt pin will be asserted if the GPIO8 status bit has been set.

Table 6.29 Interrupt Enable Registers

ADDR

R/W

DEFAULT

27h

R/W

Interrupt

Enable 1

INT_

S7_

INT_

S6_

INT_

S5_

INT_

S4_

INT_

S3_

INT_

S2_

INT_

S1_

INT_

FFh

28h

R/W

Interrupt

Enable 2

GPIO8_

INT_EN

GPIO7_

INT_EN

GPIO6_

INT_EN

GPIO5_

INT_EN

GPIO4_

INT_EN

GPIO3_

INT_EN

GPIO2_

INT_EN

GPIO1_

INT_EN

00h

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