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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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GXM датащи(PDF) 240 Page - National Semiconductor (TI) |
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GXM датащи(HTML) 240 Page - National Semiconductor (TI) |
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240 / 244 page  www.national.com 240 Revision 3.1 Index (Continued) BC_DRAM_TOP (8000h-8003h) 101 BC_XMAP_1 (8004h-8007h) 101 BC_XMAP_2 (8008h-800Bh) 101 BC_XMAP_3 (800Ch-800Fh) 101 Internal Test Signals Ifloat 32 Raw Clock 32 SDRAM Test Outputs 32 Test 33 Test Clock 32 Test Data Input 32 Test Data Output 32 Thermal Diode Negative (TDN) 33 Thermal Diode Positive (TDP) 33 Interrupt Interrupt and Exception Priorities 76 Interrupt Descriptor Table 75 Interrupt Request Level 13 25 Interrupts 74 INTR 74 NMI 74 Real Mode Error Codes 77 Real Mode, Exceptions 77 SMM 74 Vector A 75 INTR 43 , 74, 76, 83, 85, 86 invalid opcode 39 IRET instruction 43 L Legacy VGA 165 Local Descriptor Table Register (LDTR) 66 LOCK 28 Lock Prefix 39 Low Order Interleaving 112 M MediaGX™ Virtual VGA 167 Memory Address Space 60 Memory Addressing Paging Mechanism 72 Memory Addressing Modes 61 Memory Controller 103 –119 Auto LOI 112 1 DIMM Bank 113 2 DIMM Banks 113 Block Diagram 103 DRAM Address Conversion 112 DRAM Configuration 105 Graphics Pipeline 103 Memory Array Configuration 104 Memory Cycles 115 Memory Organization 105 Non-Auto LOI 1 DIMM Bank 114 2 DIMM Banks 114 Page Miss 117 Processor Interface 103 SDRAM 104 SDRAM Commands 106 ACT 107 MRS 106 PRE 106 READ 107 WRT 107 SDRAM Initialization Sequence 107 SDRAM Interface 103 SDRAM Interface Clocking 118 CAS latency 118 SDRAM Read Cycle 115 SDRAM Refresh Cycle 117 SDRAM Write Cycle 116 SHFTSDCLK 119 X-Bus 103 Memory Controller Interface Signals Bank Address Bits 29 Chip Selects 29 Clock Enable 30 Column Address Strobe 29 Data Mask Control Bits 30 Memory Address Bus 29 Row Address Strobe 29 SDRAM Clocks 30 Write Enable 29 Memory Controller Register 108 MC_BANK_CFG (8408h-840Bh) 108 MC_DR_ACC (841Ch-841Fh) 108 MC_DR_ADD (8418h-841Bh) 108 MC_GBASE_ADD (8414h-8417h) 108 MC_MEM_CNTRL1 (8400h-8403h) 108 MC_MEM_CNTRL2 (8404h-8407h) 108 MC_SYNC_TIM1 (840Ch-840Fh) 108 Memory Data Bus 29 MMX Instruction Set 229 Multiplexed Address PCI pins 26 Multiplexed Command Configuration Read 26 Configuration Write 26 Dual Address Cycle 26 Memory Read Line 26 Memory Read Multiple 26 Memory Write and Invalidate 26 Special Cycle 26 Multiplexed Command and Byte Enables Interrupt Acknowledge 26 Multitasking 70 N NMI 49 , 74, 75, 76, 78, 83, 85, 86 notebook computers 174 O Overflow Flag 43 P Package Outlines 198 Package Specifications 195 Page Table Entry 73 palette lookup 166 PCI Arbitration 164 PCI Configuration Registers Access Format 157 Bus 156 Cache Line Size (0Ch) 157 Class Code (09h-0Bh) 157 CONFIG ENABLE 156 CONFIG_DATA 0CFCh-0CFFh 156 Device 156 Device Identification (02h-03h) 157 Device Status (06h-07h) 157 Latency Timer (0Dh) 157 PCI Arbitration Control 1 (43h) 157 PCI Arbitration Control 2 (44h) 157 |
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