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GXM датащи(PDF) 239 Page - National Semiconductor (TI) |
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GXM датащи(HTML) 239 Page - National Semiconductor (TI) |
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239 / 244 page ![]() Revision 3.1 239 www.national.com Index (Continued) FPU Mode Control Register 89 Register Set 89 Status Register 89 Tag Word Register 89 FPU Instruction Set 224 Summary Notes 228 FPU Mode Control Register 90 Denormalized-operand error exception bit 90 Divide-by-zero exception bit 90 Invalid-operation exception bit 90 Overflow error exception bit 90 Precision Control Bits 90 Precision error exception bit 90 Rounding Control Bits 90 FPU Operations 89 FPU Registers 90 FPU Status Register 90 Condition code bit 3 90 Condition code bits 90 Copy of ES bit 90 Denormalized-operand error exception bit 90 Divide-by-zero exception bit 90 Error indicator 90 Invalid operation exception bit 90 Overflow error exception bit 90 Precision error exception bit 90 Stack Full 90 Top-of-Stack 90 Underflow error exception bit 90 FPU Tag Word Register (TAG7:0] 90 frame buffer 94 G Gates 87 General Purpose Registers 40 Global Descriptor Table Register (GDTR) 66 Grant Lines 29 Graphics Memory (GX_BASE+800000h) 94 Graphics Pipeline 120 –128 BitBLT/vector engine 120 Color Patterns 123 Diagonal Error Register (108h-810Bh) 124 Dither Patterns 122 Error Register (8104-8107h) 124 GP_BLT_MODE 120 GP_BLT_MODE (8208h-820Bh) 124 GP_BLT_STATUS (820Ch-820Fh) 125 GP_DST/START_Y/XCOOR (8100h-8103h) 124 GP_DST_XCOOR 121 GP_DST_YCOOR 121 GP_INIT_ERROR 121 GP_PAT_COLOR_0 register 122 GP_PAT_COLOR_1 (GX_BASE+8112h) 122 GP_PAT_COLOR_A (8110h) 124 GP_PAT_COLOR_B (8114h) 124 GP_PAT_DATA (8120h-812Fh) 124 GP_RASTER_MODE (8200h-8203h) 124 GP_RASTER_MODE (GX_BASE+ 8200h) 122 GP_RASTER_MODE Bit Patterns 123 GP_SRC_COLOR (810Ch-810Fh) 124 GP_SRC_COLOR_0 (GX_BASE+810Ch) 123 GP_SRC_YCOOR 121 GP_VECTOR_MODE (8204h-8207h) 124 GP_VGA_BASE (8210h-8213h) 125 GP_VGA_LATCH (8214h-8217h) 125 GP_VGA_READ (8200h-8203h) 124 GP_VGA_WRITE (8140h-8143h) 124 Master/Slave Registers 121 Monochrome Patterns 122 Pattern Generation 121 graphics pipeline 165 , 166 Graphics Pipeline Block Diagram 120 H HALT 25 High Order Interleaving 112 I I/O Address Space 60 Initialization 38 Initialization, CPU 38 Initiator Ready IRDY 27 TRDY 27 Instruction Fields 202 Instruction Set 39 eee Field Encoding 204 Index Field 207 Memory Addressing 205 mod base Field Encoding table 207 mod r/m Field Encoding 205 Opcode 203 prefix bytes 203 reg Field 206 s-i-b Byte 207 s-i-b present 207 sreg2 field 206 sreg3 206 ss Field 207 w Field Operand Size 203 instruction set 201 Instruction Set Format Table 202 Instruction Set Formats 201 Instruction Set Overview 39 Instructions Bit Test Instructions 39 Exchange Instructions 39 One-operand Arithmetic and Logical 39 Two-operand Arithmetic and Logical 39 Instuction Prefix Summary 203 Integrated Functions 91 Integrated Functions Programming Interface 92 Interleaving 112 Internal Bus Interface 100 –102 Internal Bus Interface Unit 640KB to 1MB 100 C-Bus 100 FPU Error Support 100 Graphics 100 IRQ13 100 L1 cache 100 Processor Core 100 Region Control Field Bit Definitions 102 Registers (GX_BASE+8000h) 101 SMI Interrupts 100 VGA Access 100 X-Bus 100 Internal Bus Interface Unit Diagram 91 Internal Bus Interface Unit Registers |
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