DS101086-10

Note 21: RSTZ transition Low-to-High occurs at the completion of the RPLLS delay or later as shown above.

Note 22: All outputs* forced low in default timing of FPD85310 during power-up delay time.

NS recommend to use the continuous download mode.

Note 25: EEPROM download occurs at first detected vertical blanking period.

Note 26: Active outputs depends on INPUT FORMAT register bits [5:6].

INPUT

FORMAT

[5:6]

VSYNC# at which

outputs go active

00

Second VSYNC

01

Third VSYNC

10

Fourth VSYNC

11

Fifth VSYNC

Note 27: When configured in ENAB Only Mode (EOM), VSYNC signals are unused except for timing EEPROM DownLoad Sequences. When configured with de-

fault values in Fixed Vertical mode, the VSYNC signal is generated any time ENAB remains low for more than 2 horizontal periods.

During Power Up, before Reset has propagated, the EEPROM may receive spurious addressing that initiates a down load sequence, but the output data is often

not captured for lack of timing alignment with VSYNC. In the case where EEPROM data is not captured during the initial (automatic) Reset or Power Up DownLoad

sequence, Timing Controller outputs are indeterminate until the EEPROM data is successfully loaded, which always begins and is executed at the next VSYNC valid

(low) cycle.

Note 28: During Power Up sequences, false RSTZ signals are possible due to instability of the power supply level, typically within the 10 ms of operation. To avoid

this situation, implementation of the circuit in

Figure 17, or other functional equivalent, is recommended, (Figure 17).

FIGURE 16. Power-up Sequence (INPUT FORMAT[6:5] = “01”)

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