HT82K96E

Rev. 1.70

24

April 22, 2004

There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB

clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK).

SCC

Bits

R/W

Function

Led_on Period

2~0

R/W

To define low pulse period of IRPT (PC0) for mouse hardware function.

The time base is 31.25

ms (1/32kHz). Default value is 000.

000: 2

´base

001: 3

´base

010: 5

´base

011: 9

´base

100: 17

´base

101: 33

´base

110: 65

´base

111: 127

´base

USBCKEN

3

R/W

USB clock control bit. When this bit is set to

²1², it indicates that the USB clock is en-

abled. Otherwise, the USB clock is turned-off. (Default=

²0²)

SUSP2

4

R/W

This bit is used for decreasing power consumption in suspend mode.

In normal mode clean this bit=0 (Default=

²0²)

In HALT mode set this bit=1 for decreasing power consumption.

¾

5

R/W Undefined, should be cleared to

²0²

SYSCLK

6

R/W

This bit is used to specify the system oscillator frequency used by MCU. If a 6MHz

crystal oscillator or resonator is used, this bit should be set to

²1². If a 12MHz crystal

oscillator or resonator is used, this bit should be cleared to

²0² (default).

HWKUPSB

7

R/W

Hardware HALT mode wake-up detect circuit active under power down mode. Low

active.

²0²: WDT timer overflow will wake-up MCU system

²1²: WDT timer overflow will start hardware wake-up detect circuit but not wake-up

MCU system.

The A/D converter implemented in the MCU is a 6-channel 8-bit A/D converter. The reference voltage (high reference

voltage and low reference voltage) can be selected as coming from external pins (PB6/VRL and PB7/VRH) or internal

power supplies of MCU (VDD and VSS). The VRL and VRH are used to set the minimal and maximal boundaries of the

full-scale range of the A/D converter. If an analog inputs, VRL or VRH is not used for A/D conversion, it also can be used

as a general purpose I/O line. The ADSC (A/D converter status and control register) register is used to set the configu-

rations and A/D clock sources of A/D converter and control the operation of A/D converter.

ADSC

Bits

Function

ACS2~ACS0

2~0

These 3 bits are use to select one of eight A/D converter channels for the conversion. The

A/D converter input channels AN0~AN5 are pin-shared with PB0~PB5. PB6/VRL and

PB7/VRH are used for the A/D converter reference inputs. ACS2,ACS1,ACS0 :

000/001/010/011/100/101/110/111: AN0/AN1/AN2/AN3/AN4/AN5/VRL/VRH

ADCS1

ADCS0

4

3

A/D converter clock source selection. ADCS1,ADCS0:

00: 6MHz

01: 3MHz

10: 1.5MHz

11: 0.75MHz

START

5

Start the A/D conversion. (0

®1®0: start, 0®1: reset A/D converter and A/D data register)

ADON

6

This bit is used to control the enable/disable of A/D converter circuit. If this bit is set to

²1²

the A/D converter enters operating mode. Otherwise, the A/D converter will be turned-off

EOCB

7

End of A/D conversion indication. (0: end of A/D conversion)

The A/D converter data register is used to store the result of A/D conversion.

ADR

Bits

Function

D7~D0

7~0

Result of A/D conversion