HT82K96E datasheet(8/46 Pages) HOLTEK

8 / 46 page

HT82K96E

Rev. 1.70

April 22, 2004

At a subroutine call or interrupt acknowledge signal, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a

²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 8 return ad-

dresses are stored).

Data Memory

- RAM for Bank 0

The data memory is designed with 190

´8 bits. The

data memory is divided into two functional groups: spe-

cial function registers and general purpose data mem-

ory (160

´8). Most are read/write, but some are read

only.

The special function registers include the indirect ad-

dressing registers (R0;00H, R1;02H), Bank register

(BP, 04H), Timer/Event Counter 0 (TMR0;0DH),

Timer/Event Counter 0 control register (TMR0C;0EH),

Timer/Event Counter 1 higher order byte register

(TMR1H;0FH), Timer/Event Counter 1 lower order byte

byte register (PCL;06H), memory pointer registers

(MP0;01H, MP1;03H), accumulator (ACC;05H), table

pointer (TBLP;07H), table higher-order byte register

(TBLH;08H), status register (STATUS;0AH), interrupt

control register (INTC;0BH), Watchdog Timer option

setting register (WDTS;09H), I/O registers (PA;12H,

PB;14H, PC;16H, PD;18H), I/O control registers

(PAC;13H, PBC;15H, PCC;17H, PDC;19H). USB/PS2

status and control register (USC;1AH), USB endpoint

interrupt status register (USR;1BH), system clock con-

trol register (SCC;1CH). A/D converter status and con-

trol register (ADSC;1DH) and A/D converter result

20H is reserved for future expanded usage and reading

these locations will get

²00H². The general purpose

data memory, addressed from 20H to BFH, is used for

data and control information under instruction com-

mands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by

²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP0 or MP1).

G e n e r a l P u r p o s e

D A T A M E M O R Y

( 1 6 0 B y t e s )

S p e c i a l P u r p o s e

D A T A M E M O R Y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

B F H

: U n u s e d

R e a d a s " 0 0 "

2 0 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

B P

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C

T M R 0

T M R 0 C

T M R 1 H

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

U S C

U S R

S C C

A D S C

A D R

B a n k 0

Bank 0 RAM Mapping

HT82K96E датащи(PDF) 8 Page - Holtek Semiconductor Inc

HT82K96E датащи(HTML) 8 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

датащи скачать

ссылки URL