CY28301
Document #: 38-07011 Rev. *C
Page 2 of 15
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
REF/FS1
56
I/O
Reference Clock /Frequency Select 1: 3.3V 14.318-MHz clock output.
This pin also serves as the select strap to determine the device operating
frequency (as described in Table 5).
X1
2
I
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency
input.
X2
3
O
Crystal Output: An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left
unconnected.
PCI0
11
O
PCI Clock 0: 3.3V 33-MHz PCI clock output.
PCI1
12
O
PCI Clock 1: 3.3V 33-MHz PCI clock output.
PCI2/SEL24_48MHz#
13
O
PCI Clock 2/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This
pin also serves as the select strap to determine the output frequency for
24_48MHz output. Logic 1 = 24 MHz on pin 35.
PCI3:7
15, 16, 17, 19,
20
O
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be
individually turned off via the SMBus interface.
3V66_0:2
6, 7, 8
O
66-MHz Clock Output: 3.3V output clocks. The operating frequency is
controlled by FS0:1 (see Table 5).
48MHz/FS0
34
I/O
48-MHz Output/Frequency Selection 1: 3.3V 48-MHz non-spread
spectrum output. This pin also serves as the select strap to determine the
device operating frequency (as described in Table 5.)
24_48MHz
35
O
24- or 48-MHz Output: 3.3V 24- or 48-MHz non-spread spectrum output.
PD#
22
I
Power-down Input: LVTTL-compatible asynchronous input that places
the device in power-down mode when held LOW.
CPU0:1
52, 51
O
CPU Clock Outputs: Clock outputs for the host bus interface. Output
frequencies depending on the configuration of FS0:1. Voltage swing is set
by VDDQ2.
SDRAM0:11,
SDRAM_F
48, 47, 46, 44,
43, 42, 40, 39,
31, 30, 27, 26,
38
O
SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The
operating frequency is controlled by FS0:1 (see Table 5).
APIC
54
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous
with the PCI clock outputs. Voltage swing set by VDDQ2.
SDATA
24
I/O
Data pin for SMBus circuitry.
SCLK
23
I
Clock pin for SMBus circuitry.
VDD_REF,
VDD_3V66, VDD_PCI,
VDD_SDRAM,
VDD_48MHz
1, 9, 10, 18, 25,
32, 37, 45, 33
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI
output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
VDD_CPU,
VDD_APIC
53, 55
P
2.5V Power Connection: Power supply for APIC and CPU output buffers.
Connect to 2.5V.
GND_REF,
GND_3V66,
GND_PCI,
GND_SDRAM,
GND_48MHZ,
GND_CPU
4, 5, 14, 21, 28,
29, 41, 49, 50,
36
G
Ground Connections: Connect all ground pins to the common system
ground plane.
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