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CY28301
Document #: 38-07011 Rev. *C
Page 13 of 15
Group Skew and Jitter Limits
Output Group
Pin-Pin Skew Max.
Cycle-Cycle Jitter
Duty Cycle
Nom. VDD
Skew, Jitter
Measure Point
CPU
175 ps
250 ps
45/55
2.5V
1.25V
SDRAM
250 ps
250 ps
45/55
3.3V
1.5V
APIC
250 ps
500 ps
45/55
2.5V
1.25V
48MHz
250 ps
500 ps
45/55
3.3V
1.5V
3V66
175 ps
500 ps
45/55
3.3V
1.5V
PCI
500 ps
500 ps
45/55
3.3V
1.5V
REF
N/A
1000 ps
45/55
3.3V
1.5V
Clock Output Wave
2.5V Clocking
3.3V Clocking
Test Point
Test Load
TPERIOD
Duty Cycle
THIGH
2.0
1.25
0.4
TLOW
TRISE
TFALL
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
1.5
0.4
Output
Buffer
Interface
Interface
Figure 1. Output Buffer