6 / 15 page
CY28301
Document #: 38-07011 Rev. *C
Page 6 of 15
Byte 2: Control Register 2
Bit
Pin#
Name
Default
Description
Bit 7
20
PCI7
1
(Active/Inactive)
Bit 6
19
PCI6
1
(Active/Inactive)
Bit 5
17
PCI5
1
(Active/Inactive)
Bit 4
16
PCI4
1
(Active/Inactive)
Bit 3
15
PCI3
1
(Active/Inactive)
Bit 2
13
PCI2
1
(Active/Inactive)
Bit 1
12
PCI1
1
(Active/Inactive)
Bit 0
11
PCI0
1
(Active/Inactive)
Byte 3: Control Register 3
Bit
Pin#
Name
Default
Description
Bit 7
8
3V66_2
1
(Active/Inactive)
Bit 6
7
3V66_1
1
(Active/Inactive)
Bit 5
6
3V66_0
1
(Active/Inactive)
Bit 4
54
APIC
1
(Active/Inactive)
Bit 3
–
Reserved
0
Reserved
Bit 2
–
Reserved
0
Reserved
Bit 1
51
CPU1
1
(Active/Inactive)
Bit 0
52
CPU0
1
(Active/Inactive)
Byte 4: Control Register 4
Bit
Pin#
Name
Default
Description
Bit 7
39
SDRAM7
1
(Active/Inactive)
Bit 6
40
SDRAM6
1
(Active/Inactive)
Bit 5
42
SDRAM5
1
(Active/Inactive)
Bit 4
43
SDRAM4
1
(Active/Inactive)
Bit 3
44
SDRAM3
1
(Active/Inactive)
Bit 2
46
SDRAM2
1
(Active/Inactive)
Bit 1
47
SDRAM1
1
(Active/Inactive)
Bit 0
48
SDRAM0
1
(Active/Inactive)
Byte 5: Control Register 5
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
38
SDRAM_F
1
(Active/Inactive)
Bit 3
26
SDRAM11
1
(Active/Inactive)
Bit 2
27
SDRAM10
1
(Active/Inactive)
Bit 1
30
SDRAM9
1
(Active/Inactive)
Bit 0
31
SDRAM8
1
(Active/Inactive)
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