M38B53M4-059FP datasheet(66/69 Pages) MITSUBISHI

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MITSUBISHI MICROCOMPUTERS

38B5 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

TIMING REQUIREMENTS

Table 16 Timing Requirements (VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, unless otherwise noted)

Min.

Typ.

Max.

Symbol

Parameter

Limits

Unit

____________

tW(RESET)

tC(XIN)

tWH(XIN)

tWL(XIN)

tC(XCIN)

tWH(XCIN)

tWL(XCIN)

tC(CNTR)

tWH(CNTR)

tWL(CNTR)

tWH(INT)

tWL(INT)

tC(SCLK)

tWH(SCLK)

tWL(SCLK)

tsu(SCLK–SIN)

th(SCLK–SIN)

Reset input “L” pulse width

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

Sub-clock input cycle time (XCIN input)

Sub-clock input “H” pulse width

Sub-clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “H” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O clock input cycle time

Serial I/O clock input “H” pulse width

Serial I/O clock input “L” pulse width

Serial I/O input set up time

Serial I/O input hold time

2.0

238

5.0

4.0

1.6

0.95

400

200

µs

SWITCHING CHARACTERISTICS

Table 17 Switching Characteristics (VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, unless otherwise noted)

Min.

Typ.

Max.

Symbol

Parameter

Limits

Unit

µs

tWH(SCLK)

tWL(SCLK)

td(SCLK–SOUT)

tv(SCLK–SOUT)

tr(SCLK)

tf(SCLK)

tr(Pch–strg)

tr(Pch–weak)

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time

Serial I/O output valid time

Serial I/O clock output rising time

Serial I/O clock output falling time

P-channel high-breakdown voltage

output rising time (Note 1)

P-channel high-breakdown voltage

output rising time (Note 2)

0.2 tc

1.8

tC(SCLK)/2–160

Test conditions

CL = 100 pF

VEE = VCC–43 V

CL = 100 pF

VEE = VCC–43 V

Notes 1: When bit 7 of the FLDC mode register (address 0EF416) is at “0”.

2: When bit 7 of the FLDC mode register (address 0EF416) is at “1”.

Fig. 73 Circuit for Measuring Output Switching Characteristics

Serial I/O clock

output port

VEE

High-breakdown

P-channel open-

drain output port

P52/SCLK11,

P53/SCLK12,

P56/SCLK21,

P57/SCLK22

P0,P1,P2,

P3,P80–P83

Note: Ports P2 and P8 need external resistors.

(Note)

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