PC87591L datasheet(180/437 Pages) NSC

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Revision 1.07

ADC Delay Control Register (ADLYCTL)

This register controls the delay between “input switching” and “conversion start” for the voltage and temperature channels.

ADLYCTL is set to A716 on reset.

Location: 00 FF2616

Type: R/W

Bit

76543210

Name

TMPDLY

Reserved

VOLDLY

Reset

10100111

Bit

Description

2-0

VOLDLY (Voltage Channel Delay). Compensates for the settling time of the input interface and externally added

ﬁlter (if used). The conversion of the VOLDLY value to delay, in terms of ADC clock cycles, is shown below. To

calculate the required value and the resulting delay time, see Section 4.11.3 on page 173 and “Calculating the

Voltage Channel Delay” on page 186.

VOLDLY Value

Bits

2 1 0:

Voltage Channel Delay (ADC Clock Cycles)

0 0 1:

0 1 0:

0 1 1:

1 0 0:

1 0 1:

1 1 0:

128

1 1 1:

256 (default)

Other:

Reserved

Reserved.

7-4

TMPDLY (Temperature Channel Delay). Compensates for the settling time of the input interface and externally

added ﬁlter (if used). The conversion of the TMPDLY value to delay, in terms of ADC clock cycles, is shown

below. To calculate the required value and the resulting delay time, see Section 4.11.4 on page 173 and

“Calculating the Temperature Channel Delay” on page 188.

TMPDLY Value

Bits

7 6 5 4 Temperature Channel Delay (ADC Clock Cycles)

0 0 0 1: 32

0 0 1 0: 64

0 0 1 1: 128

0 1 0 0: 256

0 1 0 1: 512

0 1 1 0: 1024

0 1 1 1: 2048

1 0 0 0: 4096

1 0 0 1: 8192

1 0 1 0: 16384 (default)

Other:

Reserved

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