PC87591L datasheet(179/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

179

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ADC Conﬁguration Register (ADCCNF)

This register controls the operation and global configuration of the ADC module. ADCCNF is cleared (0016) on reset.

Location: 00 FF2216

Type: R/W

ADC Clock Control Register (ACLKCTL)

This register controls the system clock to ADC clock division. ACLKCTL is set to 3F16 on reset.

Location: 00 FF2416

Type: R/W

Bit

76543210

Name

Reserved

INTOSEN

INTOTEN

INTECEN

REMDEN

ADCEN

Reset

00000000

Bit

Description

ADCEN (ADC Module Enable). Controls the operation of the ADC to minimize power consumption and prevent

glitch effects during conﬁguration changes; see “Enabling and Disabling the ADC” on page 174.

0: ADC disabled (default)

1: ADC enabled

REMDEN (Remote Temperature Diode Enable). Controls the utilization of the package pins for either the

remote diode (DP, DN) or the AI8 and AI9 voltage inputs (AD8, AD9).

0: AI8, AI9 voltage inputs enabled (default) - forces RDMEASEN in TCHANCTL register to 0; only the local diode

is measured by the temperature channel.

1: Remote diode enabled - if RDMEASEN in TCHANCTL register is set, the temperature channel measures both

the remote and the local diodes in successive cycles.

INTECEN (Interrupt from End-of-Cycle Event Enable). Enables generation of an ADC interrupt on an End-of

ADC-cycle event (EOCEV in ADCSTS register).

0: Disabled (default)

1: Enabled - ADC Interrupt from EOCEV

INTOTEN (Interrupt from Overtemperature Event Enable). Enables generation of an ADC interrupt on an

Overtemperature event (OTSEV in ADCSTS register).

0: Disabled (default)

1: Enabled - ADC Interrupt from OTSEV

INTOSEN (Interrupt from Open/Short Event Enable). Enables generation of an ADC interrupt on an

Open/Short event (OPSHEV in ADCSTS register).

0: Disabled (default)

1: Enabled - ADC Interrupt from OPSHEV

7-5

Reserved.

Bit

76543210

Name

Reserved

SCLKDIV

Reset

00111111

Bit

Description

5-0

SCLKDIV (System Clock Division Factor). Used to divide the system clock in order to obtain the ADC clock.

The system clock frequency is set separately (see Figure 78 on page 239). The resulting ADC clock frequency

should be equal to 0.5 MHz.

Range: 4 to 63 (default is 63, decimal values); values 0 to 3 are illegal and may result in undetermined ADC behavior.

7-6

Reserved.

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