PC87591L datasheet(177/437 Pages) NSC

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Embedded Controller Modules (Continued)

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An interrupt is expected from EOCEV when using the sequence listed in the EOCEV-driven ADC operation sequence (see

above). The EOCEV interrupt indicates that all four channels contain valid data and may be read. Interrupts from the

DATVAL bits should be disabled.

An interrupt is expected from one of the DATVAL bits when using the sequence listed in the DATVAL-driven ADC operation

sequence (see above). The DATVAL interrupt indicates that only its channel contains valid data that may be read. Interrupts

from the EOCEV bit should be disabled.

Failure Detection

Open/Short. At the beginning of the temperature measurement from the remote diode, the Temperature Sensor Interface

checks the condition of the interconnection (shorted or disconnected cable) and updates OPSHTYPE and OPSHEV in

ADCSTS register (see Section 4.11.6 on page 177). Although the measurement is executed and the DATVAL bit in

TCHANCTL register is set, the contents of the data buffer (TCHANDAT) should be ignored.

Overtemperature. At the end of the temperature measurement from the local diode (after DATVAL bit in TCHANCTL reg-

ister is set), the ADC compares the measured temperature with the limit value set by OTSLIM in TLOCOTL register. When-

ever the measured temperature is higher than the limit value, OTSEV in ADCSTS register is set and an active low OTS signal

is issued.

Overﬂow. An overflow occurs when DATVAL bit in TCHANCTL register is set at the end of a measurement, indicating that

the result of the previous measurement was not read. If an overflow occurs in at least one channel, the new measurement

result overrides the old data in the buffer, and OVFEV in ADCSTS register is set. This indicates that the result of the previous

measurement was lost.

4.11.6 ADC Registers

The ADC control/status and data out registers set interfaces with the core through the Peripheral bus. These registers are

mapped in the address space of the core, starting at the base address defined in Section B.1 on page 434.

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

ADC Register Map

The ADC register set contains seven common, control and status registers and eight channel-specific registers.

Table 24. ADC Register Map

Mnemonic

Type

ADCSTS

ADC Status

Varies per bit

ADCCNF

ADC Conﬁguration

R/W

ACLKCTL

ADC Clock Control

R/W

ADLYCTL

ADC Delay Control

R/W

TLOCOTL

Local Diode Overtemperature Limit

R/W

ADCPINX

ADC Parameters Index

R/W

ADCPD

ADC Parameters Data

R/W

TCHANCTL

Temperature Channel Control

Varies per bit

TCHANDAT

Temperature Channel Data Buffer

VCHN1CTL

Voltage Channel 1 Control

Varies per bit

VCHN1DAT

Voltage Channel 1 Data Buffer

VCHN2CTL

Voltage Channel 2 Control

Varies per bit

VCHN2DAT

Voltage Channel 2 Data Buffer

VCHN3CTL

Voltage Channel 3 Control

Varies per bit

VCHN3DAT

Voltage Channel 3 Data Buffer

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