PC87591L datasheet(174/437 Pages) NSC

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Embedded Controller Modules (Continued)

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To change the diode selection for a new measurement, the input is switched between inputs at different voltage levels. The

temperature input interface circuits of the ADC require a settling time to reach the new voltage value with the equivalent of

1/2

°C accuracy. Therefore, the ADC waits for a programmable delay time between the selection of the diode to be measured

and the beginning of the A/D conversion. This Temperature Channel Delay is expressed in ADC clock cycles in ADC Delay

Control register (ADLYCTL). The number of ADC clock cycles should be converted to time using the following formula:

Delay = Number_of_ADC_clocks * (System_clock_cycle) * SCLKDIV(5-0)

To calculate the required delay value according to the externally added components, see Section 4.11.7 on page 185.

4.11.5 ADC Operation

Reset

Section 3.2 on page 65 describes the types of PC87591x resets. The ADC is affected by the core domain reset events, as

described below:

All control, configuration and status registers are reset to their default values, as indicated in Section 4.11.6 on page 177.

An exception to this is OTSEV (Overtemperature Event) bit in ADCSTS register, which is reset at VCC Power-Up reset only.

The Temperature and Voltage (1, 2 and 3) Channel Data Buffer registers are not reset, since their value is undefined until

the ﬁrst measurement occurs (on each of them).

The ADC is disabled, with all interrupt sources masked and all event status bits reset. The remote temperature diode is dis-

abled, and the voltage inputs AD8 and AD9 may be used. The clock division factor, as well as the temperature channel delay

and the voltage channel delay, are all set to their maximum value (for the slowest ADC operation speed). The Overtemper-

ature limit is set to the highest value (127

°C) for maximum flexibility. Each of the four channels is individually disabled, along

with its interrupt source. The Selected Input for all three voltage channels is set to 1F16 (disabled).

ADC Clock

The ADC clock is generated by dividing the system clock by a factor in the range of 4 to 63, as defined in SCLKDIV field in

ACLKCTL register (see Section 4.11.6 on page 177). The system clock’s source is the on-chip clock multiplier (see

Section 4.18 on page 239). The ADC clock needs to be at a frequency of 0.5 MHz. SCLKDIV must be programed prior to

enabling the ADC (i.e., while ADCEN of the ADCCNF register is 0).

Initializing the ADC

The ADC must be initialized before it is enabled. The following steps need to be taken to initialize it before enabling the ADC

(i.e., ADCEN bit in ADCCNF register is cleared):

●

System Clock Division Factor - SCLKDIV ﬁeld in ACLKCTL register.

●

Temperature Channel Delay - TMPDLY ﬁeld in ADLYCTL register.

●

Voltage Channel Delay - VOLDLY ﬁeld in ADLYCTL register.

●

Select use of Remote Diode or AI8 and AI9 - REMDEN bit in ADCCNF register.

●

Copy calibration information from the ﬂash to the index-data ﬁelds using the following sequence:

a. Read a byte from ﬂash information block.

b. Set index for that parameter in ADCPINX register.

c. Write data to ADCPD register.

d. Repeat steps a-c for all parameters, as deﬁned in Section B.1 on page 434.

e. Select index 00h in ADCPINX and write data of 0116 to ADCPD to lock the calibration information.

Enabling and Disabling the ADC

Enabling the ADC. The ADC is enabled by setting ADCEN in ADCCNF register to 1.

After the ADC is enabled, its internal circuits need an activation delay of 100

µs. This activation delay should be added to

the ADC cycle until the first batch of measurements (after enabling the ADC) is available. Note that after activation, the first

set of results using the large scale mode (CSCALE bit in VCHiCTL register is clear) may be wrong.

The PC87591x temperature is measured as long as the ADC is active. Other measurement operations may be enabled or

disabled individually. When measurement conversions are enabled while the ADC is enabled, the measurement operations

start on the following conversion cycle.

Disabling the ADC. The ADC is disabled by resetting ADCEN in ADCCNF register when one of these conditions applies:

●

VCC Power-Up reset

●

Warm reset

●

Core enters Idle mode

●

The software resets the ADCEN bit.

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