PC87591L datasheet(207/437 Pages) NSC

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Embedded Controller Modules (Continued)

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ACB Control Register 3 (ACBnCTL3)

The ACBnCTL3 register expands the clock pre-scaler field and enables the match to ARP addresses. ACBnCTL2 is cleared

on reset (0016).

Location: Channel 1 -00 FF6E16

Channel 2- 00 FFEE16 (Update for Multiple Instances)

Type: R/W

4.13.9 Usage Hints

1. When the ACB is disabled, BB in ACBnCST register is cleared. After the ACB is enabled (by setting ENABLE in

ACBnCTL2 register), the bus may be in the middle of a transaction with another device in systems with more than one

master. This status is not reflected by BB.

To prevent bus errors, the ACB must synchronize with the bus activity status before issuing a request to become the bus

master for the first time. The software should check that there is no activity on the bus by checking the BB bit after the

time-out period allowed by the bus.

2. When waking up from power-down before checking MATCH in ACBnCST register, check BUSY in the same register to

make sure that the address transaction is completed.

3. The BB bit can help solve a deadlock in which two or more devices detect a usage conflict on the bus and both cease

being bus masters at the same time. In this situation, the BB bits of both devices are active (because each “detects”

another master currently performing a transaction, while in fact there is no transaction). This potentially causes the bus

to stay locked until a device on the bus sends a Stop Condition (through STOP in ACBnCTL1 register).

The BB bit allows the software to monitor bus usage so that it can detect whether the bus remains unused over a certain

period of time while BB is set. It also avoids sending a STOP signal in the middle of the transaction of another device on

the bus.

4. In some cases, the bus may get stuck with the SCL and/or SDA lines active, such as when an erroneous Start or Stop

Condition occurs in the middle of a slave receive session.

If the SCL line is stuck active, the module that holds the bus must release it.

If the SDA line is stuck active, the sequence below releases the bus (Note: In normal cases, SCL may be toggled only

by the bus master; this sequence is a recovery scheme which is an exception and should be only used if there is no other

master on the bus):

a. Disable and re-enable the module to set it for the Slave mode not addressed.

b. Set START in ACBnCTL1 register to attempt to issue a Start Condition.

c. Check if the SDA line is active (low) by reading TSDA in ACBnCST register. If it is active, issue a single SCL cycle

by writing 1 to TGSCL in the same register. If it is not active, skip to step e.

d. Check if MASTER in ACBnST register is set, which indicates that the Start Condition was sent. If it is not set, repeat

step c and this step until the SDA is released.

e. Clear BB. This enables START to be executed. Continue according to “Bus Idle Error Recovery” on page 200.

Bit

76543210

Name

Reserved

ARPMEN

SCLFRQ8-7

Reset

00000000

Bit

Description

1-0

SCLFRQ8-7 (SCL Frequency bits 8 and 7). Extends SCLFRQ ﬁeld and is concatenated with bits 0-6, which

are part of ACBnCTL2 register. Detailed use of SCLFRQ is provided in the SCLFRQ6-0 description in

ACBnCTL2.

ARPMEN (ARP Match Enable). When set, enables the matching of an incoming address byte to the SMBus

ARP address (110 00012) while the ACB is in Slave mode. When cleared, the ACB does not respond to an ARP

address.

7-3

Reserved.

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