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4.14 ANALOG COMPARATORS MONITOR (ACM)

The Analog Comparators Monitor (ACM) checks the voltage level of eight analog inputs and reports their values to the core.

The ACM can either measure the voltage of each input with 6-bit resolution or compare the level of all eight inputs with a

programmable threshold.

An operation burst includes either the voltage measurement of all inputs or one comparison check of all inputs to a fixed

threshold. The bursts may be triggered by a low-frequency clock for periodic operation.

4.14.1 Features

●

Voltage measurement

— Eight analog inputs

— 6-bit resolution

— 0V to VCC Full Scale (FS) input voltage range

— High-impedance inputs

●

Comparison check

— 6-bit threshold resolution

— Simultaneous on all inputs

●

Ratiometric measurement using VCC

●

Digital reading output

— Eight buffers for voltage value

— One buffer for comparison check

●

170

µs voltage measurement of all the inputs

●

Polling- or interrupt-driven interface

●

Power consumption

— Zero current when disabled

— Low average current in Idle mode

4.14.2 Functional Description

Inputs. The ACM has eight analog inputs with a voltage ranging from 0V to VCC (FS), as shown in Figure 74.

The voltage level at each input is compared with a reference level, generated by a 6-bit D/A converter.

Operation. The ACM can be operated in one of three modes:

●

Voltage Level Burst mode - The reference level generated by the D/A converter is ramped from 0V to FS by incre-

menting the value loaded into the converter. Whenever the ramp crosses the level of an input, its comparator toggles

state, and the D/A loaded value is latched into the corresponding Voltage Level Buffer. At the end of the ramp, exe-

cution stops and a set of eight voltage level values (one per input) is available.

●

Threshold Comparison Burst mode - A programmable value is loaded into the D/A converter, generating a constant

threshold level. A bit is set for each input if the input’s voltage level is higher than the threshold. At the end of the

single comparison, the Comparison Result register holds the status of the eight inputs.

●

Low Power Threshold Comparison mode - The inputs are periodically compared with a ﬁxed threshold. The compar-

ison is triggered by a low rate signal from the TWD module (T0IN). In addition, an interrupt is generated if at least

one input is below (or above) the threshold.

Timing. When the PC87591x is in Active or Active Executing Wait mode, ACM module timing is based on the core domain

clock (CLK). When the PC87591x is in Idle mode, timing is based on the low frequency clock (LFCLK) to minimize power

consumption.

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