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PC87591L датащи(PDF) 206 Page - National Semiconductor (TI) |
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PC87591L датащи(HTML) 206 Page - National Semiconductor (TI) |
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206 / 437 page ![]() Embedded Controller Modules (Continued) www.national.com 206 Revision 1.07 ACB Own Address Register (ACBnADDR and ACBnADDR2) The ACBnADDR and ACBnADDR2 registers hold the module’s ACCESS.bus addresses. The reset value of these registers are undefined. ACBnADDR: Location: Channel 1 - 00 FF6816 Channel 2 - 00 FFE816 ACBnADDR2: Location: Channel 1- 00 FE6C16 Channel 2- 00 FFEC16 Type: R/W ACB Control Register 2 (ACBnCTL2) The ACBnCTL2 register enables/disables the module and determines the ACB clock rate. On reset and while the module is disabled (ENABLE in ACBnCTL2 register is set to 0), ACBnCTL2 is cleared (0016). Location: Channel 1 - 00 FF6A16 Channel 2 - 00 FFEA16 Type: R/W Bit 76543210 Name SAEN ADDR Bit Description 6-0 ADDR (Address). Holds the 7-bit ACCESS.bus address of the PC87591x. When in Slave mode, the first seven bits received after a Start Condition are compared to this field (the first bit received is compared to bit 6, the next bit to bit 5 and so on until the last bit, which is compared to bit 0). If the address field matches the received data and SAEN in ACBnADDR register is set to 1, a match is declared. 7 SAEN (Slave Address Enable). When set (1), indicates that the ADDR field holds a valid address and enables the match of ADDR to an incoming address byte. When cleared, the ACB does not check for an address match. Bit 76543210 Name SCLFRQ6-0 ENABLE Reset 00000000 Bit Description 0 ENABLE. When set, the ACB module is enabled. When the Enable bit is cleared, the ACB module is disabled, ACBnCTL1, ACBnST and ACBnCST are cleared and the clocks are halted. 7-1 SCLFRQ6-0 (SCL Frequency bits 6 through 0). This field, together with SCLFRQ8-7 in ACBCTL3 register, defines the SCL’s period (low time and high time) when the PC87591x serves as a bus master. The clock low time and high time are defined as follows: tSCL =4*SCLFRQ*tCLK tSCLl =tSCLh where tCLK is the PC87591x clock cycle when in Active mode (see Section 7.6.3 on page 385). SCLFRQ may be programed to values in the range of 00 00010002 (810) through 11 11111112 (51110). Values outside this range gives unpredictable results. |
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