Input 2

1A

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

0.1 PF

AM26C31

1Y

1Z

Differential

Output 1

Input 1

2Y

2A

GND

G

2Z

4A

4Y

3Z

3Y

3A

4Z

G

Differential

Output 2

Active Low

Enable

14

AM26C31

SLLS103O – DECEMBER 1990 – REVISED JUNE 2016

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Product Folder Links: AM26C31

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Copyright © 1990–2016, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the

operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance

power sources local to the analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds, paying attention to the flow of the ground current.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as

opposed to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. Keeping RF and RG close to the inverting

input minimizes parasitic capacitance.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Figure 10. Trace Layout on PCB and Recommendations