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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP5526TL/NOPB датащи(PDF) 5 Page - Texas Instruments |
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LP5526TL/NOPB датащи(HTML) 5 Page - Texas Instruments |
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5 / 41 page  LP5526 www.ti.com SNVS431D – FEBRUARY 2006 – REVISED MARCH 2013 Electrical Characteristics (1) (2) Limits in standard typeface are for TJ = 25º C. Limits in boldface type apply over the operating ambient temperature range (- 30ºC < TA < +85ºC). Unless otherwise noted, specifications apply to the LP5526 Block Diagram with: VDD1,2 = 3.0V to 5.5V, CVDD = CVDDIO = 100nF, COUT = 2 x 4.7µF, CIN = 10µF, CVDDA = 1µF, CVREF = 100nF, L1 = 10µH, RRGB = 2.4kΩ and RRT = 82k Ω. (3) Parameter Test Conditions Min Typ Max Unit IVDD Standby supply current NSTBY = L 1.7 7 µA (VDD1, VDD2) Register 0DH=08H (4) No-boost supply current NSTBY = H, 300 800 µA (VDD1, VDD2) EN_BOOST = L No-load supply current NSTBY = H, EN_BOOST = H 780 1300 µA (VDD1, VDD2) Autoload OFF VDDA Output voltage of internal LDO IVDDA = 1mA 2.80 V -3 +3 % VREF Reference voltage (5) 1.23 V (1) All voltages are with respect to the potential at the GND pins. (2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. (3) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. (4) Boost output voltage set to 8V (08H in register 0DH) to prevent any unnecessary current consumption. (5) No external loading allowed for VREF pin. Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LP5526 |
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