LP5526

SNVS431D – FEBRUARY 2006 – REVISED MARCH 2013

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Table 11. LP5526 Control Register Names and Default Values

ADDR

REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

(HEX)

RGB_PWM

EN_RGB

CC_SW

RSW

GSW

BSW

00

Control Register

0

0

1

0

0

0

COLOR[3:0]

BRIGHT[2:0]

OVL

01

RGB

0

0

0

0

0

0

0

0

SAFETY_SE

IR[1:0]

IG[1:0]

IB[1:0]

T

02

RGB max current

0

0

0

0

0

0

0

SLOPE

FADE_SEL

EN_FADE

DISPL

EN_MAIN

EN_SUB

03

WLED Control

0

0

0

0

0

0

MAIN[7:0]

04

MAIN Current

0

0

0

0

0

0

0

0

SUB[7:0]

05

SUB Current

0

0

0

0

0

0

0

0

EN_PWM_P

OEN[2:0]

IN

06

GPIO Control

0

0

0

0

DATA[2:0]

07

GPIO Data

0

0

0

NSTBY

EN_BOOST

EN_FLASH

EN_AUTOL

OAD

0B

Enables

0

0

0

1

BOOST[7:0]

0D

Boost Output

0

0

0

0

1

0

0

0

EN_SAFET

EN_SAFET

EN_SAFET

EN_EXT_R_

EN_EXT_G_

EN_EXT_B_

EN_MAIN_P

EN_SUB_P

Y_R

Y_G

Y_B

PWM

PWM

PWM

WM

WM

2B

PWM Enable

0

0

0

0

0

0

0

0

LP5526 Register Bit Explanations

Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:

Table 12. Register Bit Accessibility and Initial Condition

Key

Bit Accessibility

RW

Read/write

R

Read only

–0,–1

Condition after POR

30

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